If the EC responds to the AP with IN_PROGRESS, the AP will then use
GET_COMMS_STATUS to poll for completion of the previous command.
If the EC doesn't support GET_COMMS_STATUS, it will return an error,
confusing the AP.
BUG=chrome-os-partner:20978
TEST=flashrom on Pit
BRANCH=pit
Original-Change-Id: I7c911ebc047042450b1eefc992ba2250d35fa078
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66702
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 67efd2c100f9de6fe34d381f6145e2d795d8549f)
Change-Id: If102710d30cbc53670bb5652b473734c7d9251be
Reviewed-on: https://gerrit.chromium.org/gerrit/66827
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
The registers.h file should only be included by code in the chip/ and
board/ directories. Code outside those directories should not access
chip-specific registers.
(This change doesn't completely fix that, because
common/extpower_usb.c uses STM32-specific regs, but we'll fix that in
a separate CL.)
BUG=chrome-os-partner:18343
BRANCH=none
TEST=compile all platforms
Change-Id: Ic499f56690c38663083423b0593800161a68e6e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64382
Reviewed-by: Vic Yang <victoryang@chromium.org>
Remove support for allowing host command handlers to set the response
pointer. This is just one more thing that can break (and did, on SPI
protocol V2). No commands other than the trivial read-memory-map
command in host_command.c and flash read made use of this capability,
and the savings in performance was negligible.
BUG=chrome-os-partner:21576
BRANCH=none
TEST=boot pit; still boots
Change-Id: I0a9bcf57dbea7155318fc389d7b47d3742a1a00a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64236
This adds two new fields: the ideal write size for best EC flashing
performance (e.g., page mode instead of word mode), and a flags field
with a flag to indicate whether the EC erases its bits to 0 or 1.
The EC still supports the old version 0 command, since u-boot and
flashrom expect that to work.
BUG=chrome-os-partner:20973
BRANCH=(all haswell); this will speed up flashing and software sync
TEST=ectool flashinfo
1. old EC, new ectool -> only reports version 0 info
2. new EC, old ectool -> only reports version 0 info
3. new EC, new ectool -> reports new fields
Change-Id: I484327fe22a58d2b69d7f6ac767b2d3e81b3e0b7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62378
Reviewed-by: David Hendricks <dhendrix@chromium.org>
STM32L erases flash to 0, not 1, so we need a config value to indicate
that. This speeds up flash erase on STM32L by not re-erasing
already-erased blocks.
BUG=chrome-os-partner:13066
BRANCH=none
TEST=manual - hack flash_physical_erase() to print something just after
flash_is_erased() check.
1. flasherase 0x1f800 0x800
2. flashwrite 0x1fa00 0x100
3. flasherase 0x1f800 0x800 -> only re-erases 0x1fa00
Change-Id: I4d726caf0605e7815b9360bb2d44bdfdd757b4a2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61110
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Version 1 of EC_CMD_FLASH_WRITE will use as big a write as possible given
the available command parameter space. Falls back to 64 byte writes on old
platforms.
BUG=chrome-os-partner:20571
BRANCH=none
TEST=Copy burn_my_ec onto a link and run it. Write size should be 64 bytes
for the first half of the update (since the old EC doesn't support ver.1
of the write command) and 240 bytes for the second half of the update.
Change-Id: I5900de3a5700d7c82a2e0c3cf9921b7ced1c0343
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60511
Previously, code which needed to work on all STM32F platforms needed
to specify them by name (CHIP_VARIANT_stm32f100 ||
CHIP_VARIANT_stm32f10x), and we needed extra symlinks in the
chip/stm32/ directory to allow the build system to find
family-specific files.
Add a CHIP_FAMILY level of abstraction, so that things which are
common across all STM32F platforms don't need to specify every STM32F
variant. Make the chip build look for family-specific filenames
instead of variant-specific filenames (except for config*.h, which is
actually variant specific).
In the few places where things actually are variant-specific, keep
using the existing CHIP_VARIANT defines.
Code refactoring only; no functional changes.
BUG=chrome-os-partner:20567
BRANCH=none
TEST=build all platforms
Change-Id: I1da831aadabf8b8dd9dfde423cac13c9f43eb953
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60247
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The ec driver does not yet pass the command version properly from app
to the EC. This causes a failure when trying to read flashrom write
protect status (command 0x15).
The thing is that the command version is not even important for this
command, as it was never implemented differently.
As a quick fix - mark the command descriptor as supporting both
versions.
BRANCH=none
BUG=chromium:239197
TEST=manual
. on peach_pit (with fixed flashrom, coming under a separate fix):
# flashrom -p ec --wp-status
flashrom v0.9.4 : : on Linux 3.8.11 (armv7l), built with libpci 3.1.10, GCC 4.7.x-google 20130114 (prerelease), little endian
WP: status: 0x00
WP: status.srp0: 0
WP: write protect is disabled.
WP: write protect range: start=0x00000000, len=0x00000000
#
Change-Id: I8302457cc2afdfe3bdcb50cfa2bea29969d0c107
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59462
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The firmware defines had two almost-identical sets. Coalesce into one
consistent set.
Link had 256 KB flash, but only allowed 2 80KB images. Future
LM4-based platforms (slippy/peppy/falco/etc) will now use the entire
flash, with RO=124KB, pstate=4KB, RW=128KB. This matches what the
STM32 platforms do, where pstate is contiguous with the RO firmware.
No functional change to STM32-based platforms.
BUG=chrome-os-partner:19176
BRANCH=none
TEST=build all platforms and dump_fmap ec.bin.
- stm32-based platforms should report RO=61440@0, RW=65536@0x10000
- link should report RO=81920@0, RW=81920@0x14000
- slippy should report RO=129024@0, RW=131072@0x20000
Change-Id: I20b1d95c16250d9a5d228ead06eef03d96548823
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56655
Persistent state is needed by all platforms to hold the
protect-ro-at-boot flag. STM32F100 and LM4 implementations were
near-identical, and are now common code (with one #ifdef to handle the
single place where they weren't).
STM32L doesn't use pstate yet, but it'll need to. I can't simply
store the protect-ro-at-boot flag inside the WRP registers themselves
because they're still writable in EC-RW. The change to STM32L to use
pstate is coming next.
BUG=chrome-os-partner:15613
BRANCH=none
TEST=build pit, link, spring; on link and spring, do
- flashinfo -> (no flags)
- enable WP (via screw or dut-control)
- flashinfo -> wp_gpio_asserted
- flashwp enable
- flashinfo -> wp_gpio_asserted ro_at_boot
- flashwp now
- flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now)
- flashwp disable -> fails
- flashinfo -> wp_gpio_asserted ro_at_boot all_now
- reboot ap-off
- flashinfo -> wp_gpio_asserted ro_at_boot ro_now
- disable WP (via screw or dut-control)
- reboot
- flashinfo -> ro_at_boot
- flashwp disable
- flashinfo -> (no flags)
(Note that on Spring you'll need to 'forceen on' before enabling WP,
or the console will be disabled once you enable ro_at_boot and reboot.)
Change-Id: I415388b98ec8bf1d149803aaaa7fe8c7f3076c36
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56064
This adds support for write protecting the RO code at boot, and the
entire flash on demand.
Implementation if WP# is not asserted is currently a little different
than STM32F and LM4; RO is still protected at boot if ro_at_boot, but
can be unprotected and the change will commit on the next reboot.
This saves the bank of flash which we use for pstate on LM4 and
STM32F. I think I can use one of the unused option bits (WRP2 bit 0)
to hold the RO-at-boot flag, in which case I can more closely match
the behavior of the other chips, but I'd like to do that (or give up
and implement pstate) in a separate CL so it's clearer what I'm doing.
BUG=chrome-os-partner:15613
BRANCH=none
TEST=manual
- flashinfo -> (no flags)
- enable WP (via screw or dut-control)
- flashinfo -> wp_gpio_asserted
- flashwp enable
- flashinfo -> wp_gpio_asserted ro_at_boot
- flashwp now
- flashinfo -> wp_gpio_asserted ro_at_boot all_now
- flashwp disable -> fails
- flashinfo -> wp_gpio_asserted ro_at_boot all_now
- flasherase 0x1fc00 0x400 -> fails
- reboot
- flashinfo -> wp_gpio_asserted ro_at_boot ro_now
- flasherase 0xfc00 0x400 -> fails
- flasherase 0x1fc00 0x400 -> succeeds
- disable WP (via screw or dut-control)
- reboot
- flashinfo -> ro_at_boot ro_now
- flashwp disable
- flashinfo -> ro_now
- reboot
- flashinfo -> (no flags)
- flasherase 0xfc00 0x400 -> succeeds
- flasherase 0x1fc00 0x400 -> succeeds
Change-Id: Id1b6b099a44a1985a5ab9387feb882a8f26e3aa1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/55594
CONFIG_ macros should be set directly. Expanding the task names in the same
way made it difficult to tell what was a configuration choice and what was
due to changes in ec.tasklist
BUG=chrome-os-partner:18343
TEST=build all, run link
BRANCH=none
Change-Id: Ib82e34f974238ee2dd216f33b701b6f4c6a4f1f1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49098
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This merges flash_overwrite and flash_rw_erase to a single test binary.
BUG=chrome-os-partner:18598
TEST=Run on Spring
BRANCH=None
Change-Id: I1da7577cb5dc196178930dda3a07bb942d959866
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48090
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the entire flash is protected (as it normally is after software
sync), fail all flash write/erase operations.
Add a shadow copy of the all_now flag.
BUG=chrome-os-partner:16727
BRANCH=link
TEST=manual
Verify that flash operations work properly before all_now. Then enable HW WP
and
flashwp enable
flashwp now
and try
flasherase 0x38000 0x1000
flashwrite 0x38000 0x100
Those commands should fail with error 7
From the host side
ectool flasherase 0x38000 0x1000
echo 'Khaaaaaaaaaaan' > /tmp/b16727
ectool flashwrite 0x38000 /tmp/b16727
should also fail.
Change-Id: I99a4d2bb86080bd12c900582a8fbdfc79c99916c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39517
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
No functional changes; just clean up comments and remove dead code
BUG=chrome-os-partner:15579
BRANCH=none
TEST=code compiles
Change-Id: Id006ae18f2b26cea1720196f696f937811b6ba5b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36448
Reviewed-by: Simon Glass <sjg@chromium.org>
Current *_RW_NOW/RW_AT_BOOT is used to lock the entire flash. This could
lead confusion in the future. So, rename them.
Since the bit definition is unchanged, thus the callers (u-boot, flashrom)
is fine if they don't change the name.
BUG=chrome-os-partner:12951
BRANCH=snow,link
TEST=build in chroot only:daisy,snow,link,bds
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Change-Id: I2395e93793f590e6fb8aae7006eb8e5c836002bc
Reviewed-on: https://gerrit.chromium.org/gerrit/31199
Commit-Ready: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
Tested-by: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It wastes time to erase blocks that are already erased and it is faster
on stm32 to check first. Add a check in flash_physical_erase() on all
chips, using a common flash_is_erased() function.
BUG=none
BRANCH=snow,link
TEST=manual
Do software sync in U-Boot and see that it succeeds. This tests that
we can still erase and then boot a written image. It typically saves
a second on a full sync over i2c.
SMDK5250 # cros_test swsync -f
SF: Detected W25Q32 with page size 4 KiB, total 4 MiB
Flashing RW EC image: erasing, writing, done
Flashing RO EC image: erasing, writing, done
Full software sync completed in 22.949s
SMDK5250 #
Also see that second erase is faster:
SMDK5250 # time mkbp erase rw
time: 0.952 seconds, 952 ticks
SMDK5250 # time mkbp erase rw
time: 0.054 seconds, 54 ticks
SMDK5250 #
Change-Id: I3699577217fdbb2f212d20d150d3ca15fdff03eb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/30851
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Erasing the flash can take a while, by which time the host may have timed
out. So pass an in-progress message back to the host before starting, and
when done, stash the result for later collection.
BUG=chrome-os-partner:12685
BRANCH=snow,link
TEST=manual
build and boot to kernel on snow
Change-Id: I5566a5519a1c8b320573b20e1ea7660217b32a5e
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/30471
To reflect the CL 00799d5 that moves the pstate to 0xf000.
BUG=chrome-os-partner:12799
TEST=Build in chroot.
snow: WP_RO is changed from 0:0xf000 --> 0:0x10000.
daisy: WP_RO is unchanged.
link: WP_RO is unchanged.
Change-Id: I572bae3f624744e60d13a762875211beffc6c516
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/30670
Reviewed-by: Vic Yang <victoryang@chromium.org>
Adds shmem command to print amount of shared memory. This is also a
useful indicator of how much IRAM is left, since shared memory will
expand to fill all unused IRAM.
Removes never-implemented wait param to shared_mem_acquire().
BUG=none
TEST=shmem
Change-Id: I798ff644d701dcba52219b70bec99c06a23d03ec
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/29809
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This removes a bunch of unnecessary typecasts, since you can assign
to/from void * without them. This also uncovered a few cases where
const was being cast away for the input params; now fixed.
BUG=none
TEST=mkbp hash from u-boot console, and/or system boots ok
Change-Id: Ic314b9d2ca06226ea8a09703ef5c1a912eb7146d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/28500
This is a significant rewrite of the flash module, since it turns out
that much less of the flash logic is actually common between stm32 and
lm4.
BUG=chrome-os-partner:11699
TEST=on link,
(enable hardware wp)
flashinfo -> wp_gpio_asserted
flashwp enable
flashinfo -> wp_gpio_asserted ro_at_boot
reboot
flashinfo -> wp_gpio_asserted ro_at_boot ro_now
flashwp disable -> error 7
flashwp now
flashinfo -> wp_gpio_asserted ro_at_boot ro_now rw_now
reboot
flashinfo -> wp_gpio_asserted ro_at_boot ro_now
(disable hardware wp)
reboot
flashinfo -> ro_at_boot
flashwp disable
flashinfo -> (no flags)
Change-Id: If22b02373946ce1c080d49ccded4f8fa3e380115
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/28200
Reviewed-by: Vic Yang <victoryang@chromium.org>
Everything now uses flash_dataptr() to get at flash memory rather than
calling the read function, since the read function adds a needless memcpy().
BUG=chrome-os-partner:11150
TEST=manual
flashwp enable
reboot
flashinfo -> should show ro_at_boot
flashwp disable
reboot
flashinfo -> should no longer show ro_at_boot
Change-Id: I1830e2f036cf6777115c782c1737335ff2eb4ce0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27796
Since that already monitors the WP signal for reporting it as a
switch. And if we have that code in two places and the WP signal
polarity changes, we'll inevitably forget to change it in the other
place...
BUG=chrome-os-partner:11150
TEST=manual
flashinfo -> WP pin asserted
remove WP screw
flashinfo -> WP pin deasserted
Change-Id: I6091c8bb470c357e02ede8a5b184b2a76b70dc60
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27720
Now that read-only code is protected iff the persistent state is
locked, we don't need to track per-block in the persistent state.
BUG=chrome-os-partner:11150
TEST=if it builds and boots, it's fine
Change-Id: I80e6a85c0c72136b7ed8964ce02c8abdbaafe637
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27719
1. If the flash protection state is locked, RO firmware is explicitly locked.
2. Protecting flash now locks the entire flash.
BUG=chrome-os-partner:11150
TEST=manual
flashinfo -> nothing protected
flashwp now
flashinfo -> unlocked,applied; everything protected
reboot
flashinfo -> nothing protected
flashwp lock ->
flashinfo -> locked,applied; now has 40 Y's at start and 1 at end
reboot
flashinfo -> locked,applied; now has 40 Y's at start and 1 at end
remove WP screw
reboot
flashinfo -> locked, not applied; nothing protected
flashwp unlock
flashinfo -> nothing protected
Change-Id: I2cf0e8bfe82ab7a5bf88b9161b7a05b889cae71a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27717
Uncomment back the old code and fix the bug of WRP bit definition and
also write_opt().
Note that to make this functional, wp_pin_asserted() always returns true.
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Change-Id: Ic09d3346ca68a2700697ff863f0fa08525129b11
BUG=chrome-os-partner:9849
TEST=run on lucas.
> flashwp set 0 0x1f000
> flashwp lock
> flashinfo # ensure the setting is right.
stm32mon -r to read the firmware.
stm32mon -w to write a different image.
stm32mon -r to read again and compare the firmware is non-changed.
> flashwp unlock
Command returned error 1
stm32mon -u to unlock write protection.
Reviewed-on: https://gerrit.chromium.org/gerrit/27503
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
If flash starts at zero, then flash_dataptr() will return NULL for a valid
region. Change the function around so that it can be used in this case.
BUG=chrome-os-partner:10146
TEST=manual:
Modify code it print out parameters and problems, then:
Writing 256 bytes to 0x0...
0 256 64
ok 131072
Command returned error 1
> flashwrite 0 256
Writing 256 bytes to 0x0...
0 256 64
ok 131072
Command returned error 1
> flashwrite 0 255
Writing 255 bytes to 0x0...
0 255 64
Command usage/param invalid.
Usage: flashwrite offset [size]
Change-Id: I5683fc181ef780310ceff50f120735659e973784
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26749
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Sometimes it is useful to get access to the flash directly, without using
flash_read(). Add a function to do this.
Since the range checking is done in every function in flash_common,
use the new function to do it for us. That way we get a slight (64 byte)
code size reduction.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow with SPI flash emulation, in U-Boot:
See that the 32KB of flash has been provided correctly.
Change-Id: I6622a24234edaed371dd5b9bf43d1f3974d55e39
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26174
This simplifies the re-flashing for stm32 based platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=On Daisy, flashrom -p internal:bus=lpc -w ec.bin
Change-Id: I66860383c34110b1edf852929c244a2b682bc105
The VMA of the .data segment is in RAM, but we actually put it into FLASH.
The linker doesn't notice if it runs out of flash, so it creates an invalid
image.
This adds an explicit check to be sure it all fits. It also refactors the
region declarations to be more explicit. For vboot-enabled configurations,
CONFIG_SECTION_* - describes the extent of flash for one entire image
CONFIG_FW_* - the region within the SECTION for the firmware only
CONFIG_VBLOCK_* - the region within the RW SECTIONs for the vblocks
CONFIG_VBOOT_ROOTKEY - the region within the RO SECTION for the root key
Look at chip/lm4/config.h for the best example.
BUG=chrome-os-partner:9839
TEST=manual
Build it, run it.
Change-Id: I3c652e82d58a5328115cc750c80ecba6a3fd99a3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Implements the on-chip flash erasing and writing functions.
The actual writing is done from a routine in internal RAM (using the
special .iram.text section) with interrupt disabled as we cannot read
flash during the writing process.
The write-protect feature is only lightly tested.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=run on Daisy, from the EC console, use flasherase and flashwrite
commands and observe the results using rw command.
Change-Id: I4c64cf28b23df52b18500b42a32a7d3668d45ba6
Servo2 can set the write protect signal
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8580
TEST=manual
From chroot:
dut-control fw_wp_en:on
dut-control mfg_mode:on
Then from EC console:
gpioget WRITE_PROTECTn
0 WRITE_PROTECTn
From chroot:
dut-control fw_wp_en:on
dut-control mfg_mode:off
Then from EC console:
gpioget WRITE_PROTECTn
1* WRITE_PROTECTn
Change-Id: I9976cd6f114c8dae75434adf99d9409107b6ada0
This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
