I pushed the wrong version of my previous CL I6384024a,
a warning prevents the spring board from building successfully.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:14313
TEST=make BOARD=spring
BRANCH=none
Change-Id: If0b088daf7e3db7615fb778f3289d7fd7cf69f2a
Reviewed-on: https://gerrit.chromium.org/gerrit/33700
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
the PMU VACG signal used to detect AC state is connected to a GPIO, so
it's a board specific configuration.
On top of that, Daisy variants have custom logic on that line which is
not present on the next boards, so we need to update it before doing BSP
for next-gen boards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:14313
TEST=make BOARD=snow && make BOARD=daisy
on snow EC console, type "pmu" command with AC plugge and unplugged, see
that the "ac gpio" line reflects the right value.
BRANCH=none
Change-Id: If1e19b89b2f2de45d8dddc8340931e56c5f7f0a5
Reviewed-on: https://gerrit.chromium.org/gerrit/33630
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This calibration has been done with black tape covering the screw in front of
the sensor to reduce machine to machine variability.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9599
TEST=compare to thermocouple measurement on a couple of Link DVT
machines at various operating points.
BRANCH=link
Change-Id: I3664acd49eaae788823a4ca87173c108659ede8c
Reviewed-on: https://gerrit.chromium.org/gerrit/33527
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
The old spi driver has atrophied in various ways. It doesn't support
the new protocol and does not build either.
Rewrite the driver to:
- Use dma for reception (rather than just reception)
- This makes message reception more robust and allows us to process
the new multi-byte commands
- Add timeouts for rx and tx so that we don't wait forever
- Increase buffer sizes to deal with new larger messages
- Always send a preamble byte regardless of SPI clock speed
(previously above 10MHz we sometimes miss this)
- Use the NSS line to delineate transactions. When it drops, a
transaction is starting. When it rises the transaction is immediately
terminates regardless of state. This keeps the AP and EC in sync even
in the event of timeouts, bus errors and other oddities.
- Implement the new protocol which has a checksum, version byte, etc
- Set up tx dma in advance and kick it when ready, thus ensuring that
a message body is always attached immediately after the preamble
- Use the new host_cmd_handle_args structure, which makes things much
easier for us, since we don't need globals, and can use the
send_response handler to know when a slow command is complete.
- Handle the new type of 'slow' commands properly
BUG=chrome-os-partner:10533
TEST=manual
build and boot to kernel on snow
Change-Id: I11767d1a6f045a86f6c9a0b4b1e943b660e4da33
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32076
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Haven't found a use for these, so remove to reduce code size (reduces
binary by 2KB) / complexity.
These are still test-compiled on BDS so they'll be ready if needed.
BUG=chrome-os-partner:11232
BRANCH=link
TEST=build and boot firmware. 'help' should not show eeread/eewrite commands
Change-Id: I0f2e41e21efcbbb0967a5b85b7c8a2ff8147460e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/33112
Reviewed-by: Simon Glass <sjg@chromium.org>
This removes sensors U10, U13, U15, and U29
BUG=chrome-os-partner:13274
BRANCH=link
TEST=temps command should show only USB, PCH, hinge, charger die/object temps
and PECI should still be the 10th temp sensor
Change-Id: If33266ad87ec06a8d4272009d80e382fa4003e2b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32822
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This logic doesn't really belong in drivers, since to enable another
driver (like SPI) we must repeat it all. This is tricky if we enable
both I2C and SPI.
Move the logic into host_command.
BUG=chrome-os-partner:10533
BRANCH=none
TEST=manual
Use U-Boot to test comms status functionality on snow:
SMDK5250 # mkbp write rw 40000000
SMDK5250 # mkbp erase rw
SMDK5250 # mkbp erase rw
Change-Id: I3f90aada80208cd0540be14525f73f980ad33292
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32075
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Increase stack size slightly for vboot hash task since the vboot
SHA256 function allocates ~300 bytes of stack data. Reduce stack size
for watchdog, power LED, and a few other tasks with simple call trees
where we can be sure an error path isn't going to blow past the
reduced stack.
This frees up ~1KB of RAM on STM32.
BUG=chrome-os-partner:13814
BRANCH=all
TEST=boot system; shmem should show more unused RAM; taskinfo should show
tasks still have unused stack
Change-Id: I47d6b77564a0180d15d86667cc0566a8919b776e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32608
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This (re-)configures the I2C arbitration lines as floating inputs
when the AP powers off, and restores them strictly before the AP
powers on. This is intended to prevent leakage when the AP is off
and arbitration is not needed. This CL does not impact the AP
on/suspend case.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:12573,chrome-os-partner:12381
TEST=manual (see notes below)
- PA4: SPI1_NSS / AP_CLAIM, input w/ pull-up when AP on
- PA6: SPI1_MISO / EC_CLAIM, output when AP is on
- Both floating when AP off
8 = input with pull up/down, 4 = floating input, 1 = output
AP off (before this CL):
> rw 0x40010800
read 0x40010800 = 0x41484144
> gpioget SPI1_NSS
0* SPI1_NSS
> gpioget SPI1_MISO
1 SPI1_MISO
AP off (after this CL):
> rw 0x40010800
read 0x40010800 = 0x44444144
> gpioget SPI1_NSS
0* SPI1_NSS
> gpioget SPI1_MISO
0* SPI1_MISO
AP on or suspended (before and after this CL):
> rw 0x40010800
read 0x40010800 = 0x81484144
> gpioget SPI1_NSS
1* SPI1_NSS
> gpioget SPI1_MISO
1* SPI1_MISO
Additional testing:
- "pmu 10000" and "cros_test i2c" in u-boot only showed the FET2
control changing (as expected).
- "pmu 10000" and "while [ 1 ] ;
do i2cdump -f -y -r 0-24 4 0x48 b ; done" and ran
"suspend_stress_test" for a couple dozen iterations. The
registers only changed as expected (FET1 and FET6 turned off
when suspending).
Change-Id: I72f5cb1883d01b1faad6c2db65dfa09d477e1885
Reviewed-on: https://gerrit.chromium.org/gerrit/32078
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
The TMP006 IR sensors are calibrated against the temperature measured on
the *external* side on the casing using a thermocouple stick at the
vertical of the sensor.
The hinge sensor is sending back strange values, and the Tobject from
there should not be trusted.
The DC-Jack C-case sensor is not calibrated (and will be removed soon).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Link DVT, compare EC temperature values against thermocouple
readings.
BRANCH=link
Change-Id: I03375dd1c2f3a0aa56b0d2f343dad3b8f7581bc2
Reviewed-on: https://gerrit.chromium.org/gerrit/32156
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Old Snow board (non-MP) don't have the capability to hard-reset their
pmics unless they've been manually fixed to do so. This means that if
you have an old board, with a new copy of the EC on it and it tries to
hard-reset the system, it will hang forever and trigger the watchdog.
Since there's no way for the EC to check if the hardware fix exists on
its board, this adds a timeout after trying to reset. If the board has
the fix, it will reset before the timeout expires. Otherwise, it will
print a warning message before returning, to prevent it hanging.
Additionally, it also fixes the places board_hard_reset() is called to
deal with the new possibility of it returning.
BUG=chrome-os-partner:13508
TEST=On a machine with the hardware rework and one without it, go to the
EC console and run "pmu reset" to try and force a reset. The one with
the fix should reset immediately, and the one without should warn you
that it tried (and failed) to reset.
BRANCH=snow
Change-Id: I493122ee4da539f363a31f624ab9dd7db8068ec8
Signed-off-by: Charlie Mooney <charliemooney@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32043
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that the panic stack goes at the end of RAM, there's no overhead
to using it on all platforms. When it was a dedicated block of
memory, we needed to turn it off on some low-RAM platforms
(e.g. Snow).
BUG=chrome-os-partner:7466
TEST='crash divzero' or 'crash unaligned'; should print dump and reboot
BRANCH=all
Change-Id: Iddfeb134e237538215df51abe4e16ee831b3ae2d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/32037
Reviewed-by: Simon Glass <sjg@chromium.org>
BUG=chrome-os-partner:13439
BRANCH=snow
TEST=manual
1. Ctrl+Refresh+Esc; should go to INSERT screen
2. Ctrl+D; should show TODEV (this confirms it's still possible to get into
dev mode the right way)
3. From EC console, 'sysjump rw'
4. Ctrl+D; should NOT show TODEV (this confirms the bug is fixed)
Change-Id: Ic4879cb0a7fc47527eac1a5a727f3225744ff880
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/31932
This re-factors i2c initialization to simplify it and make it follow
the correct order. This is intended to fix a bug where the I2C lines
could be driven low for no good reason on EC startup, potentially
causing issues with other devices.
The ordering should be:
1. Setup pins as inputs on EC startup.
2. Initialize I2C module(s)
3. Re-configure pins as alternate function.
(Thanks to dianders for pointing out this bug)
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:13443
TEST=Tested by examining scope traces during EC reboot
Change-Id: Ibb845f3fd538da387132b1c822929f8613de077d
Reviewed-on: https://gerrit.chromium.org/gerrit/31647
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
By pulling line gio_A15 high, you can for a hard reset of the pmic after
the stuff resistor is changed. This change adds a function that you can
call from the EC and trigger this event (board_hard_reset). The user has
access to this command over the EC console by running "pmu reset" and
it will force the emergency reset.
The board_hard_reset function is used in the pmu's reset code. Whenever
it is trying to initialize or shut down the pmu, it resets many or all
of its registers over i2c. If the i2c commands fail to get a response
from the pmu, the EC will now force a hard reset of the system, which
restores everything, allowing for a restart to fix any situation where
the pmu has gotten its configuration trashed.
BUG=chrome-os-partner:12913
TEST=boot the machine. From EC console check the pmic's register
values, then alter them. Run "pmu reset" to force a reset, and check
the values again. They should be safe values, which you can confirm
by powering on the AP. Repeat this from various starting states: only
the EC on, AP on as well, and setting various registers to 0x00's and
0xff's. To stress test the hard-reset ability from the EC's POV, run
while true; do echo "pmu reset"; sleep 5; done | cu -l DEVICE -s 15200
BRANCH=snow
Change-Id: I911fb9623a7c106d1f993ee4681258c05d4dedae
Signed-off-by: Charlie Mooney <charliemooney@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/31524
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds hooks to re-configure SUSPEND_L (GPIO PA7) when the system
turns on/off. When the system is turned on, PA7 will have its internal
pull-up enabled. This is required since SUSPEND_L is driven by an open-
drain buffer. When the AP is off, we can disable the pull-up
(configure PA7 as floating input) to reduce leakage.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:12700,chrome-os-partner:13200
TEST=see notes below
1. Dump GPIO_A CRL when system is off:
read 0x40010800 = 0x41484144
2. Dump GPIO_A CRL when system is on:
read 0x40010800 = 0x81484144
3. Dump GPIO_A when system is put into suspend:
read 0x40010800 = 0x81484144
4. Resume, see power LED react quickly.
5. Soft poweroff, dump GPIO_A CRL:
read 0x40010800 = 0x41484144
Change-Id: I62f02324a2a1fbfb6eff539fc6fdc35a035fa020
Reviewed-on: https://gerrit.chromium.org/gerrit/31315
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
The cut-off command is manufacturer-specific. Thus the logic is implemented
in gas gauge IC code. For those boards using this gas gauge, define
the CONFIG_BATTERY_BQ20Z453 in board.h.
BUG=chrome-os-partner:12962,
BRANCH=snow
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
TEST=Tested on snow
ectool batterycutoff ; expect system is off immediately
; if AC power is not connected.
Change-Id: Idd290c76439f3263c1c812b236b79623878f73b2
Reviewed-on: https://gerrit.chromium.org/gerrit/31466
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Yung-Chieh Lo <yjlou@chromium.org>
Tested-by: Yung-Chieh Lo <yjlou@chromium.org>
When battery temperature t in range 0C to 10C, default charging current
is 50%. And it will take longer than 3 hours to charge battery from 0%
to full.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:13172
TEST=manual
Check pmu register 0x4. FASTCHARGE bits[4:2] should be 0b100.
Change-Id: I133acee21c0886b0739b4b41766ca077bb4babbc
Reviewed-on: https://gerrit.chromium.org/gerrit/31458
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
TPSCHROME NTC readings didn't match battery gas gauge temperature. The
charging was turned off by TPSCHROME too early, and was resumed too
late.
This change disables TPSCHROME thermal protection in T40 by set charging
voltage and current to 100%.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:12221
BUG=chrome-os-partner:13171
TEST=manual
Check pmu register settings. VSET/ISET are equal in T23,T34,T40
ranges.
Change-Id: Ic60cc2bf606ed02496aad80b02360a19efafd3c0
Reviewed-on: https://gerrit.chromium.org/gerrit/31457
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
EC won't be accessing BIOS SPI, so no need to compile in this code.
BUG=chrome-os-partner:11232
TEST='spi' command on EC console should no longer be valid
BRANCH=link
Change-Id: I09d5e99dbe1fd63cb7839454030067d29249a9ed
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/31516
Reviewed-by: Vic Yang <victoryang@chromium.org>
Only setup the arbitration GPIOs when CONFIG_ARBITRATE_I2C is set.
BUG=chrome-os-partner:13064
BRANCH=snow
TEST=manual
build and boot on snow
On the EC:
> pmu 1000
In U-Boot:
cros_test i2c
See that there are no failures.
Change-Id: I8a7724700ff79406527c3db8708833728eb9a978
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/31305
This feature is not actually used on current platforms. Avoid setting
up the GPIO unless it is specifically enabled.
BUG=chrome-os-partner:13064
BRANCH=snow
TEST=manual
build and boot on snow. See the AC power GPIO does not change when
un/plugging power.
Change-Id: I6731625a19f30f6dd35471b126f3083b39747203
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/31304
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The existing state machine does the following:
- when power button is pressed it
1. powers on the AP
2. sets a timer of 1 sec and then
3. waits for power button to be released
When the timer fires it checks xpshold is set by the AP and if so
it clears the pwron signal (which is used by the AP to detect power
button is pressed).
The problem occurs when the user holds the power button for more than a
second. The AP turns on xpshold, then notices that pwron is still on
and subsequently powers down because it thinks the power button is
pressed. When the button is finally released, since it was held down
for more than a second, the timer routine notices that xpshold is not on
and therefore shuts down the system.
Another problem found while analysing this state machine is that loop
checking for poweroff only triggers on the rising edge of xpshold. This
means that if the AP powers down the EC might miss a possible power
event.
Here is the proposed fix:
When the power button is pressed the EC will:
1. power on the AP
2. Check for xpshold to be asserted with a 1 sec timeout
3. If uboot is healthy xpshold should come on pretty quickly; the EC
then waits for the power button to be released in less than 8 seconds
4. If the power button is released then the EC waits for power off
events.
5. If the power button is not released it waits for upto 8 seconds
before turning off the AP.
The added wrinkle is how to address a borked uboot case. In the case
where xpshold doesn't come on in < 1 second, the EC will allow the AP to
stay on for upto 16 seconds so that USB boot can finish. The user must
hold the power button down until uboot boots and sets xpshold. The
assumption here is that USB boot takes < 16 seconds.
BUG=chrome-os-partner:12748
TEST="follow instructions in bug report"
Change-Id: I5b582a6c3ae3449238e2813e4a581bd8f92dd846
Signed-off-by: Puneet Kumar <puneetster@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/31291
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The ec used to have to check the state of the AP since it would leave
the arbitration lines when it suspended. That meant you couldn't trust
the arbitration lines without checking the power state. Now the AP
pulls the arbitration lines high when it suspends, so it no longer needs
to test this when trying to acquire master.
BUG=chrome-os-partner:12460
TEST=First, on the EC console run "battery" and "pmu" to make sure they
work. Then repeat those steps after putting the AP in suspend by
running powerd_suspend, they should still work. Then shutdown the
machine entirely and try them again. Note: pmu needs the AP to be on to
work, so if it fails here that's okay, just make sure it's not an
arbitration error.
BRANCH=snow
Change-Id: I335156bbce4888949111f74e8a83fe9d184a7a63
Signed-off-by: Charlie Mooney <charliemooney@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/30906
Reviewed-by: Jon Kliegman <kliegs@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
USART1 has always had its Tx and Rx pins configured as "alternate
function output". However, this turns out to be incorrect since
there is no concept of an AF input on the STM32F. Instead, the
Rx pin should be configured as an input (and the Tx remains an
AF output).
This also simplifies the console resume code since we only need to
enable/disable the interrupt rather than reconfiguring the GPIO.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:12223
TEST=flashed on snow, EC console works
Change-Id: Ia92dbbac16fc55d0db62381dfb487aeb4f4121b4
Reviewed-on: https://gerrit.chromium.org/gerrit/30941
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Usually the power LED is driven by the PWM mode so that its nominal
brightness can be set to a "soft" on value. However, when
the LED is to remain off the LED should be switched to floating
input mode. This reduces voltage leakage.
This CL updates the power_led_task to configure the LED however is
appropriate and adds board functions to re-configure the GPIO.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:12381
TEST=LED responds as expected in suspend and on/off states, also
tested that leakage is reduced with multimeter
Change-Id: If90ac78aaffe7358cce80dd02ec1423c2cb4f664
Reviewed-on: https://gerrit.chromium.org/gerrit/29705
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This change corrects charger interrupt event handling, charger enable
gpio, battery full condition, EC deep sleep mode support when AC
unplugged, and lid controlled power off.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BRANCH=snow
BUG=chrome-os-partner:12573,12574,12575
TEST=manual
- ec console command 'gpioget':
- SPI1_MISO should be 0 when AP off
- CHARGER_EN should be 0 after AC unplugged
- charging led should be off after AC unplugged
- when battery remaining charge < 3%, system should be powered off
without AC.
- ec console command 'sleepmask 0', turn off AP:
- deep sleep only when AC unplugged
Change-Id: I0f63835dae67d90de7a8c8c6c3537ca9a16faed4
Reviewed-on: https://gerrit.chromium.org/gerrit/30316
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Changes made by this patch:
1. Create IRQ handler for the TPS65090 IRQ. IRQ wakes up charger task.
2. Charger task sets the AC_STATUS GPIO based on the AC status.
3. Initialize PMU at power-on.
BRANCH=snow
BUG=chrome-os-partner:11739
TEST=Power on the system, with servo v2 connected to EC console. Plug
and unplug AC. The IRQ handler should be triggered.
Change-Id: Ice23411c275111fdb56d2c47ba28c3c44dee4d71
Signed-off-by: Simon Que <sque@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/29914
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
When the AP is not running and we have enough time go to STOP mode
instead of simple idle.
The EC consumption should drop from 12mW to a few mW.
This is currently not activated by default, you need to type "sleepmask
0" in the EC console to activate it.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8866
TEST=on Snow, check the software is still working properly when STOP
mode is activated and measure power consumption on 3v_alw rail.
Change-Id: I231d76fe6494c07b198c41694755b82d87c00e75
Reviewed-on: https://gerrit.chromium.org/gerrit/29315
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Superseded by EC software sync (hash-based).
Sig-based vboot was correctly implemented, but ended up being too slow
to be useful given the limited processing power of the EC chips, and
we also couldn't come up with a manageable way to handle A/B
autoupdate of signed EC firmware.
This change and an associated vboot_reference change shrinks the EC
binary by ~2KB.
BUG=chrome-os-partner:11232
TEST=build link,snow; boot link and check that 'hash' command still works.
Change-Id: I3f03ae2d0a4030977826980d6ec5613181e154c2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/29496
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We need a bit more internal RAM for verified boot hash feature,
let's de-activate RAM hungry debug features.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:12271 chrome-os-partner:10895
TEST=make BOARD=snow
check RAM size with CONFIG_VBOOT and CONFIG_VBOOT_HASH activated.
Change-Id: I4d1d6c0f99a8b03011af6eb2d73455beba93c535
Reviewed-on: https://gerrit.chromium.org/gerrit/29278
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This was implemented for Daisy a long time ago, but left out on Snow
due to some confusion.
GPIO remapping is already handled because PD1 and PD0 (which is used
for ENTERING_RW) are remapped together. So all we need here is the
board_keyboard_suppress_noise() function definition which gets
called from the keyboard scanning code whenever a change is detected.
BUG=none
TEST=Verified using a scope that CODEC_INT line is driven
when a key is pressed (15us pulse)
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ifd358eb89a9547c4f4b9536b8922c93d2c3b77a0
Reviewed-on: https://gerrit.chromium.org/gerrit/28989
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BDS has been slowly rotting as we make changes for Link. I haven't been able
to test the BDS image for some time (I think due to openocd updates that no
longer like the BDS configs), and now it doesn't even compile. This is
gating the Link schedule, so I'm just turning it off. If we ever need the
BDS again, well, what fun.
BUG=none
TEST=none
It already doesn't work, so it should continue to not work.
Change-Id: I2b365623903590a56948dfceb986a2300699f541
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/28181
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When system is off or suspended, board_i2c_claim() should not wait
for AP's signal.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:11285
TEST=manual
Put AP into suspend
Type 'i2c r 0x90 0' and see that no arbitration error is obtained.
Change-Id: I22243457fc29bc6c88f413ce0660c700e54f6761
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27498
And retain compatibility for old requests.
BUG=chrome-os-partner:11275
TEST=from u-boot prompt, 'mkbp hash'
from root shell, 'ectool flashread 0 68084 /tmp/foo'
then compare to first 68084 bytes of ec.bin
Change-Id: Id82068773703543febde79fc820af7486502e01f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27226
The spec of link internal battery pack changed. This CL adds
parameter for new pack, and renames vendor specific source file
accordingly.
The new trickle charging current limit should fix the slow
pre-charging issue.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:11298,10201
TEST=manual
The minimum trickle charging current should be very close to
0.01 C (85mA). Previous battery pack firmware uses 5mA in pre-
charging.
Change-Id: I0bad679db7dd087894297e6eb0e85c9b12fdf444
Reviewed-on: https://gerrit.chromium.org/gerrit/27256
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
We choose PE2/USB1_CTL1 for BOOTCFG. If we somehow brick the EC, we can
pull this signal to ground and boot EC into boot loader to recover it.
BUG=chrome-os-partner:8769
TEST=On link:
- Factory reset EC to clear BOOTCFG
- Flash new EC binary and reboot
- rw 0x400fe1d0 to check BOOTCFG value is correctly written
- Boot normally and check EC is operating correctly
- Pull the signal to ground and reset EC, check EC stays in boot
loader. Check in this case we can program EC.
- Attempt to write different value to BOOTCFG and check BOOTCFG
doesn't change.
Change-Id: Ia6705114d495b18bd7ee4afc1e61e84a21b51198
Reviewed-on: https://gerrit.chromium.org/gerrit/27000
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
