Pin rename only; no functional changes. See also b/72426192 for
earlier functional changes.
BUG=b:77301519
TEST=make -j buildall
BRANCH=none
Change-Id: I18e71118e584a5b36ba001bac24951929d2c93ff
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1087207
Reviewed-by: Edward Hill <ecgh@chromium.org>
This patch configures the GPIO pin connected to the reset pin of
Anx7447 as push-pull low. When the EC start up from reset, it
pulls it high, waits for 1 msec, then pulls it low. This allows the
tcpc to recover from a hang and guarantees it to start from a known
state.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:79868559
BRANCH=none
TEST=Verify Anx7447 port charges on Nami with a rework.
Change-Id: Ib7683e20160edf0f320a8c6af25f5f74d4f74538
Reviewed-on: https://chromium-review.googlesource.com/1077015
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
we do not need to configure alt function on GPIOC2 to get PWM1
functionality. alt function here actually means I2C6_SCL0 and that
also affects the function of GPIOC1/I2C6_SDA0 which is definitely not
what we want.
BUG=b:94613023
BRANCH=none
TEST=able to power-off the AP
Change-Id: I68abfb7e8c64faffbe0cea0a2cc8ca6a4a620ba3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1086469
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Set the GPIO output driving the PCH interrupt as push-pull as the other
side has a 100K pull-down.
No longer modify the GPIO config in S3, the PCH doesn't seem to work
this way, but needs to be confirmed.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78613978
TEST=On Meowth, monitor /proc/interrupts before and after suspend/resume
cycle, no more interrupt storm on Int 46 / chromeos-ec.
Change-Id: I6198412d791ed9810ffa208fffbb8f378421decd
Reviewed-on: https://chromium-review.googlesource.com/1032775
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
It matches the SS path, in which both port-0 and port-1 connect to the
hub.
BRANCH=none
BUG=b:74395451
TEST=Tried plugging USB 2.0 disk to port-0 and port-1, both bootable.
Change-Id: Ic0264657fbe126242a419ef33ce07bc2599375ee
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1082981
Reviewed-by: Douglas Anderson <dianders@chromium.org>
The EC needs to enable/disable the NVMe power rails on bootup and
shutdown. This commit just adds these controls in during chipset
startup and shutdown.
BUG=b:73258414
BRANCH=poppy
TEST=Flash nocturne, verify that rails come up on boot up and are turned
off on shutdown.
Change-Id: I3dc8c17255294c0bbf8638ea3ee3fcfaa321929b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1067947
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
these changes reflect the hardware changes made between version 0 and
version 1 of the atlas board.
note: these changes are not backward compatible - version 0 of atlas
is no longer supported.
BUG=b:78309559
BRANCH=none
TEST=works fine on atlas version 1
Change-Id: Ia519f161c66066e02e9ddce7560a8fe2b7e74882
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1045730
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Currently, the power LED pulses in sleep state on Pantheon. This patch
makes it blink with 25% duty. That is, the LED turns on for 1 sec then
turns off for 3 sec.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:79733195
BRANCH=none
TEST=make BOARD=nami
Change-Id: I0ebd2778b9b6551f2313ea8f8648c69324e02368
Reviewed-on: https://chromium-review.googlesource.com/1069337
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Split battery info between baseboard and board, following the
Octopus example. This will allow Grunt and Careena to define their
own lists of supported battery types.
This also adds CONFIG_BATTERY_REVIVE_DISCONNECT support, and
checks the charge/discharge FET status.
BUG=b:79704826,b:74018100
BRANCH=none
TEST=Grunt still boots ok.
Change-Id: I6e82ac5e48f9aabf59b63add253108513f0a6b60
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072039
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The default setting of the ROP PMIC's V085A output voltage is incorrect
for our application. This commit changes the output voltage to actually
be 0.85V.
BUG=b:80271678
BRANCH=poppy
TEST=Flash nocturne and verify that V085A is ~0.85V.
Change-Id: I3c6c7396bc8b896620aab7e4719f8a14b4a46e4a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1077085
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The factory reset command can be used to enable ccd factory mode. The
command can open ccd if write protect is removed and ccd hasn't been
restricted. Right now we check FWMP and the ccd password before allowing
factory reset. Factory reset cannot be used to get around anything that
disables ccd.
This adds 72 bytes.
BUG=b:77543904
BRANCH=cr50
TEST=Try enabling factory mode using factory reset. Verify setting write
protect, setting the FWMP disable ccd bit, or setting a ccd password
prevents factory reset from enabling factory mode.
Change-Id: I6e203bf6068250f009881aa95c13bc56cb2aa9e7
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069369
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch makes Sona follow the standard LED pattern for single LED
systems. Sona has two LEDs but both are connected to the same pin.
This increases userbility because LEDs are visible from each side
and users don't have to learn two different sets of patterns (i.e.
one for left LED and onother for right LED).
* Charging Amber on (S0/S3/S5)
* Charging (full) White on (S0/S3/S5)
* Discharge in S0 White on
* Discharge in S3/S0ix Alternate pulse (up-down-off-off)
* Discharge in S5 Off
* Battery Error Amber on 1sec off 1sec
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:80135370,b:74940319
BRANCH=none
TEST=Verified LED behaviors in S3, S0, charge, discharge on Sona
Change-Id: I1bd53c7c60529a8b813eabc338876af6d089ec82
Reviewed-on: https://chromium-review.googlesource.com/1074226
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jack Huang <jachuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We're doing a bit of refactoring to break out factory mode into its own
file. Now factory reset and rma reset will be two methods of entering
factory mode. Factory mode can be disabled with the disable_factory
vendor command.
Factory mode means all ccd capabilities are set to Always and WP is
permanently disabled. When factory mode is disabled, all capabilities
are reset to Default and WP is reset to follow battery presence.
This adds 56 bytes.
BUG=none
BRANCH=cr50
TEST=verify rma reset will enable factory mode.
Change-Id: I21c6f7b4341e3a18e213e438bbd17c67739b85fa
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069789
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Using the p256 curve is beneficial, because RMA feature is currently
the only user of the x25519 curve in Cr50, whereas p256 support is
required by other subsystems and its implementation is based on
dcrypto.
The p256 public key is 65 bytes in size, appropriate adjustments are
being made for the structure storing the server public key and the key
ID.
The compact representation of the p256 public key requires 33 bytes,
including the X coordinate and one extra byte used to communicate if
the omitted Y coordinate is odd or even.
The challenge structure communicated to the RMA server allows exactly
32 bytes for the public key. To comply, the generated ephemeral public
key is used in compressed form (only the X coordinate is used).
For the server to properly uncompress the public key one extra bit is
required, to indicate if the original key's Y coordinate is odd or
even. Since there is no room for the extra bit in the challenge
structure, a convention is used where the generated ephemeral public
key is guaranteed to have an odd Y coordinate.
When generating the ephemeral key, the Y coordinate is checked, and if
it is even, generation attempt is repeated.
Some clean up is also included: even with debug enabled, generated
challenge is displayed only once as a long string, convenient for
copying and pasting.
The new feature is not yet enabled, p256 support on the RMA server
side is not yet available.
Enabling p256 curve for RMA authentication saves 5336 bytes of the
flash space.
BRANCH=cr50, cr50-mp
BUG=b:73296606
TEST=enabled CONFIG_RMA_AUTH_USE_P256 in board.h, generated challenge
and verified matching auth code generated by the rma_reset
utility.
Change-Id: I857543c89a7c33c6fc2dc00e142fe9fa6fc642cf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1074743
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have determined the checks to run for board_is_first_factory_boot.
This change updates cr50 to check for those conditions and enable ccd
when the system determines that it is first boot in the factory. This
will check that the board id is erased and the inactive image is a GUC
image.
The factory updates Cr50 from the GUC image, because those GUC images
don't have support for everything they need to do in the factory. To
determine that cr50 just recovered from that factory update, it will
check that the GUC image is still in the inactive region and no board id
is set.
There are 2 images installed in GUC 0.0.13 and 0.0.22, so cr50 will
check these versions. Future GUC images will have a field in the header
declaring that they are a GUC image. I still need to create the GUC
field in the header and check that in inactive_image_is_guc_image.
Factory mode can't be enabled on deep sleep resume. It is only enabled
after power-on reset or hard reset.
This change also moves factory stuff into a factory_mode file instead of
keeping it in board.c
This adds 200 bytes.
BUG=b:77543904
BRANCH=cr50
TEST=Verify factory mode is only enabled when cr50 recovered from
reboot not deep sleep resume, 0.0.13 or 0.0.22 are in the inactive
region, and the board id is erased.
Change-Id: Ibece878049658493e8ad159121ada63d7a6f6b79
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1059864
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
we normally try to find out a few things about a battery (like charge
level) before actaully applying charging power to it. when the
battery is completely discharged, the controller on the battery can't
respond as it is not self-powered. so, we have to avoid all
operations that depend on the battery responding in the battery
discovery/initialization path.
as long as we report that a battery is present and it is not
responsive, the charger task will enter ST_PRECHARGE which means it'll
provide a "precharge" current to the battery to try to talk to it.
this allows the battery's controller to report battery parameters
allowing our charger task can do the right thing.
BUG=b:79354967
BRANCH=none
TEST=atlas now discovers the discharged battery reliably
Change-Id: I5e5a3abda07508eb791b712fb2f9b9f5fe383e07
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065492
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Decreases verification time from 923ms to 785ms.
Optimized version do not really help in RW, as they just increase
the image size (which also increases verification time).
BRANCH=fizz
BUG=b:77608104
TEST=make BOARD=fizz -j, flash fizz, check timing.
Change-Id: Ia8c36c35c0321c1995dc1cede7b27f7636037795
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1075908
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Since the PS8751 is now driving the EN_SNK GPIO on the PPC, we cannot
reset without a battery otherwise we will brown out the board.
BRANCH=none
BUG=b:78896495,b:78021059
TEST=verified with reworked board.
Change-Id: Ibadf46de922c49f5fdd08c43991e71f852ff7600
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067711
Saves another ~1300 bytes of flash size, as the touchpad
hashes can now be computed in blocks of 4K, instead of 1K.
This costs 3K of SRAM, which we would not otherwise need on
hammer.
wand can only fit 2k PDU, so let's stick to that.
Also, make sure that util/gen_touchpad_fw is regenerated when the
configuration option changes (touchpad FW size, PDU size). Sadly,
this will still break bisection from commit after this CL, to
before this CL.
BRANCH=poppy
BUG=b:80167548
TEST=make buildall -j
TEST=make BOARD=hammer/staff/wand/whiskers all tests -j
TEST=Copy new staff image with old touchpad FW to DUT, verify that
FW can be updated.
Change-Id: Ic1763684da730dc986bbbcb3312088c8208c84b5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070953
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some tests cannot be built on some boards (not enough SRAM,
unusual configuration, etc.). Instead of the long list of
exceptions in test/build.mk that we currently use, allow
each board (or chip) build.mk to set test-list-y, and
only use the default list if it is unset.
BRANCH=poppy
BUG=b:80167548
TEST=make buildalltests -j
Change-Id: I803c691f419451aad4396529302a4805cbe3f9b5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1074572
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There are still more ifdef than can be added: this just takes out
the low hanging fruits.
BRANCH=poppy
BUG=b:35647963
TEST=make buildall -j, see that we gain from 0 to 64 bytes on many
boards.
Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070948
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In rare cases, it is useful to be able to build tests for all boards:
buildall only builds the main image, but -paladin builders also builds
test cases for each board.
Also remove/fix tests for boards that currently fail.
BRANCH=none
BUG=b:35647963
TEST=make buildalltests -j, wait a long time, tests pass.
Change-Id: Id6d978705a40a2045731cb08ad2ca5d62cc12ebb
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072218
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow setting password from the AP, but not from USB. Remove the old
password control logic, which is no longer needed.
Allow open if:
- Not explicitly blocked
- Not blocked via FWMP
- One of the following is true:
- A password is set
- Battery is removed (also doesn't require physical presence)
- Dev mode is on, and request came from the AP
Reduces cr50 binary by 152 bytes.
BUG=b:79983505
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 build
ccd oops
ccd lock
ccd unlock -> fails
gsctool -U -> fails from host
gsctool -t -U -> fails from AP
ccd oops
ccd password foo -> fails from console
gsctool -P -> fails from host
gsctool -t -P -> works from AP
ccd get -> confirms password set
ccd lock
ccd unlock foo -> works
ccd lock
gsctool -U -> works from host, if correct password supplied
ccd lock
gsctool -t -U -> works from AP, if correct password supplied
ccd open foo -> works
ccd lock
gsctool -O -> works from host, if correct password supplied
ccd lock
gsctool -t -O -> works from AP, if correct password supplied
ccd oops
ccd lock
(remove battery)
ccd open -> works without physical presence
(reattach battery)
ccd lock
gsctool -O -> works from host
ccd lock
gsctool -t -O -> works from AP, if dev mode is enabled
Change-Id: I364b322d03db250e7dd140767d7a22dbb3ac1eef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072957
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Move code that will be common to Grunt and Careena to baseboard
to avoid duplication when creating the Careena board.
Add Careena board files. These are currently just a copy of Grunt
and will be modified for Careena next.
BUG=b:79704826
BRANCH=none
TEST=Grunt still boots ok.
Change-Id: I6dd0035bdd62e92a7f3664120fc6ac3f23a0af4d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070988
Saving space in RW, even if we are not critical in terms of size,
always helps to reduce verification time.
BRANCH=poppy
BUG=b:35647963
TEST=make newsize => Hammer shrinks by ~3k, verification time
down by ~12 ms.
Change-Id: I63741106fdc56c410871fb367c29605bf37f1b77
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070951
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the changes made to tcpci for alert handling and low power mode
entry, the anx7447 can operate with auto toggle and low power config
options.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:77544959
BRANCH=none
TEST=Verfied that low power mode is entered when nothing is attached
and that when an adapter is attached it connects and when removed
returns to low power mode.
Change-Id: I9c683c3f86ba98e55748ac355b3d4845799d89e5
Reviewed-on: https://chromium-review.googlesource.com/1049061
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org>
Enable PWM control of backlight in EC for yorp and phaser. Proto build
of bip will not have backlight control in EC.
BRANCH=none
BUG=b:79422226
TEST=none (no hardware to test with)
Change-Id: Ib6ed4af4de3145b112ed43b4ca1ec9f931f3875f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1050785
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The ITE eval board relied on the chip's define for LPC. Since the ITE
chip supports both LPC and eSPI, we want to define LPC here to be
explicit.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ic477277543c1f24999070dc408052c7266df22e6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067501
Reviewed-by: Randall Spangler <rspangler@chromium.org>
