Add support to enable the architectural D-cache on ARMv7-M CPU
supporting it.
Update the MPU code in order to be able to declare an 'uncached' RAM
region (e.g. to store the DMA buffer).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78535052, b:75068419
TEST=with the following CL, on ZerbleBarn, boot and capture a finger
image.
Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285
Reviewed-on: https://chromium-review.googlesource.com/1032776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We're doing a bit of refactoring to break out factory mode into its own
file. Now factory reset and rma reset will be two methods of entering
factory mode. Factory mode can be disabled with the disable_factory
vendor command.
Factory mode means all ccd capabilities are set to Always and WP is
permanently disabled. When factory mode is disabled, all capabilities
are reset to Default and WP is reset to follow battery presence.
This adds 56 bytes.
BUG=none
BRANCH=cr50
TEST=verify rma reset will enable factory mode.
Change-Id: I21c6f7b4341e3a18e213e438bbd17c67739b85fa
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069789
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Using the p256 curve is beneficial, because RMA feature is currently
the only user of the x25519 curve in Cr50, whereas p256 support is
required by other subsystems and its implementation is based on
dcrypto.
The p256 public key is 65 bytes in size, appropriate adjustments are
being made for the structure storing the server public key and the key
ID.
The compact representation of the p256 public key requires 33 bytes,
including the X coordinate and one extra byte used to communicate if
the omitted Y coordinate is odd or even.
The challenge structure communicated to the RMA server allows exactly
32 bytes for the public key. To comply, the generated ephemeral public
key is used in compressed form (only the X coordinate is used).
For the server to properly uncompress the public key one extra bit is
required, to indicate if the original key's Y coordinate is odd or
even. Since there is no room for the extra bit in the challenge
structure, a convention is used where the generated ephemeral public
key is guaranteed to have an odd Y coordinate.
When generating the ephemeral key, the Y coordinate is checked, and if
it is even, generation attempt is repeated.
Some clean up is also included: even with debug enabled, generated
challenge is displayed only once as a long string, convenient for
copying and pasting.
The new feature is not yet enabled, p256 support on the RMA server
side is not yet available.
Enabling p256 curve for RMA authentication saves 5336 bytes of the
flash space.
BRANCH=cr50, cr50-mp
BUG=b:73296606
TEST=enabled CONFIG_RMA_AUTH_USE_P256 in board.h, generated challenge
and verified matching auth code generated by the rma_reset
utility.
Change-Id: I857543c89a7c33c6fc2dc00e142fe9fa6fc642cf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1074743
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ID pins are considered additional KSOs while keycode scanning works
for the existing KSI0 ~ KSI7. While diriving ID pins, the state of
interconnection between ID pins and KSI pins could be used for
identifiers to tell keyboard itself. (e.g. US, Japan,and UK keyboard)
BRANCH=master
BUG=b:80168723
TEST="make -j buildall"
TEST=Verified 5 distinct keyboard samples w/ different Language ID values
on the same reworked Coral, which VOL_UP and VOL_DOWN were reworked
for ID pins. crrev.com/c/1053617 is my experimental patch on top of
this for further verification
Change-Id: I1d6e647df74c50d60bc1264c045b2587d0bf23d8
Signed-off-by: paris_yeh <pyeh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068951
Commit-Ready: Paris Yeh <pyeh@chromium.org>
Tested-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Use a queue now for sync events, this will allow multiple interrupts to be
called before the motion sense task executes. The events (including
timestamps) get stored in a small queue. 8 events for the queue size should
be plenty, most applications will have latency concerns anyway once we
get a couple of queued up events.
Also changed the init function to be a little bit more robust to race
conditions. Added count argument to the "sync" simulation command to test
the queue behavior.
BRANCH=master
BUG=b:73551961, b:67743747
TEST="sync 4" yields 4 events on the AP, whereas before it would only
give the AP the last event.
Change-Id: I9fcb1fb8b35eb5f8ffcc21afbfcb0f0d9bc33804
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065149
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
We multiply 2 32-bit numbers (and not 64-bit numbers), and then add
another 32-bit number, which makes it possible to optimize the
assembly and save a few instructions.
With -O3, 3072-bit exponent, lower verification time from 122 ms to
104 ms on STM32F072 @48Mhz.
Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>.
BRANCH=poppy
BUG=b:35647963
BUG=b:77608104
TEST=On staff, flash, verification successful
TEST=make test-rsa, make test-rsa3
TEST=Flash test-utils and test-rsa to hammer => pass
Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449024
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There are still more ifdef than can be added: this just takes out
the low hanging fruits.
BRANCH=poppy
BUG=b:35647963
TEST=make buildall -j, see that we gain from 0 to 64 bytes on many
boards.
Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070948
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On hammer, we do not need the console channels, so we can just
disable them to save flash size.
BRANCH=poppy
BUG=b:35647963
TEST=make newsizes, staff image size shrinks by 704 bytes
Change-Id: I7a493ae57573814b166d45e57f1ad3d885f26086
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070949
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Introduce CONFIG_HOSTCMD_LPC and CONFIG_HOSTCMD_ESPI which will replace
CONFIG_LPC and CONFIG_ESPI. Today the CONFIG_LPC option guards both
common code to eSPI and LPC and LPC-only code. Going forward
CONFIG_HOSTCMD_LPC will guard only LPC code, and a new option
CONFIG_HOSTCMD_X86 will guard common code to both LPC and eSPI.
I am leaving the CONFIG_LPC and CONFIG_ESPI defines in this CL so each
CL in the stack compiles.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I6ae3a805167a3404701d8a53c14dc83299afb376
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067498
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When EC sees voltage drops below BAT_LOW_VOLTAGE_THRESH,
we kick off a timer and ask AP to throttle.
When the timer expires which means EC hasn't seen under-voltage
for BAT_UVP_TIMEOUT_US, we ask AP to stop throttling.
We reset the throttling status and do nothing when AP is off (S5).
BUG=b:73050145, chromium:838754
BRANCH=scarlet
TEST=manually test on scarlet, confirm EC sends
EC_HOST_EVENT_THROTTLE_START and EC_HOST_EVENT_THROTTLE_STOP
host events when entering/exiting UVP.
Change-Id: Ia760989f760f95549f7a8a8acb1d01de23feab5a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1064983
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
sleepmask is really useful for debugging sleep issues. Add a read only
version of sleepmask to non-DBG images. It will only be accessible once
the console is unlocked.
BUG=none
BRANCH=cr50
TEST=make sure sleepmask can be modified in DBG images and can only be
read in prod images.
Change-Id: I31ef966f6302d4a7602a014cb08c9b972d13f41e
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1062804
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Make Esc+Refresh+Power on Grunt enter Recovery Mode.
If Power is released fast:
[0.045303 KB init state: -- 02 08 -- -- -- -- -- -- -- -- -- --]
Add CONFIG_KEYBOARD_IGNORE_REFRESH_BOOT_KEY to handle this case.
If Power is held longer:
[0.045448 KB init state: 08 0a 08 08 08 -- 08 -- 08 08 -- 08 08]
Add CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3 to handle this case.
BUG=b:79758966
BRANCH=none
TEST=Esc+Refresh+Power gives recovery screen on Grunt
Change-Id: I43a7d485535ff7b0d9bfce59f28c0049ee989818
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1063032
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
This patch promotes board/nami/keyboard_backlight.c to common
directory.
Board customization is done via board_kblight_init callback.
It currently supports two drivers: direct PWM control and lm3509.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:78360907,b:78141647
BRANCH=none
TEST=On Nami (for lm3509) and Sona (pwm), verify the followings:
1. Alt + brightness up/down works
2. After suspend-resume, brightness is restored
3. Lid close/open
4. After screen is off, keyboard backlight is turned off
Change-Id: I584c06e8702fe7b289999698f277311cfd3400bd
Reviewed-on: https://chromium-review.googlesource.com/1051027
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
When EC sees discharge current hit BAT_MAX_DISCHG_CURRENT,
we kick off a timer and ask AP to throttle.
Then EC keeps monitoring discharge current. If the current doesn't
drop below BAT_MAX_DISCHG_CURRENT - BAT_OCP_HYSTERESIS, we restart
the timer and notify AP again, which shouldn't happen unless
AP misses or ignores the first notification.
When the timer expires, which means EC hasn't seen over-current
for BAT_OCP_TIMEOUT_US, we ask AP to stop throttling.
BUG=b:74321682, chromium:838754
BRANCH=scarlet
TEST=manually test on scarlet, confirm EC sends
EC_HOST_EVENT_THROTTLE_START and EC_HOST_EVENT_THROTTLE_STOP
host events when entering/exiting OCP.
Change-Id: I1e55fc23249596d8afec52a3885655ca9c1f2151
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/994188
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
This patch adds an interrupt handler for a tablet switch and an init
hook to enable the interrupt.
The handler does the typical tasks for convertible devices: 1. sets
tablet mode then 2. disables peripherals if tablet mode is on.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77298177
BRANCH=none
TEST=buildall. Verify on Nami.
Change-Id: If7fb5ea15f388d2b6084d800d2bc05efafd1945e
Reviewed-on: https://chromium-review.googlesource.com/1043057
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Port 0:
TCPC: ANX3429
PPC: SN5S330
BC1.2: PI3USB9281
Port 1:
TCPC: PS8751
Power switch (sink): NX5P3290
Power switch (source): NX20P5090
BC1.2: PI3USB9281
Charger: ISL9238
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests:
* Plugged adapter to port-0/port-1/both and saw charging
* Plugged USB device to port-0/port-1/both and saw sourcing VBUS
* Plugged adapter to one port and USB device to another port
* Plugged USB disk to port-0 and booted into kernel
* When AP off, not sourcing VBUS to USB device
* Rebooting AP still works
Change-Id: Icde5e24c2cda3d0f2046486528a210af84befcca
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969701
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
We add a configuration option to set the minimum shared memory
size (CONFIG_SHAREDMEM_MINIMUM_SIZE), so that the link will fail
if there is not enough IRAM left.
Also, we add 2 macros around shared_mem_acquire, that check, at
build time, that the shared memory size is sufficient for the
allocation:
- SHARED_MEM_ACQUIRE_CHECK should be used instead of
shared_mem_acquire, when size is known in advance.
- SHARED_MEM_CHECK_SIZE should be used when only a maximum size
is known.
This does not account for "jump tags" that boards often add on
jump from RO to RW. Luckily, RW usually does not do verification,
and does not need as much shared memory.
BRANCH=none
BUG=chromium:739771
TEST=make buildall -j, no error
Change-Id: Ic4c72938affe65fe8f8bc17ee5111c1798fc536f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1002713
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is the power sequence for rev-0 board. Confirmed the behavior of
reprogramming the PMIC registers to enable the instant reset and
shutdown.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Tried the following cases:
* Cold reset:
$ dut-control cold_reset:on sleep:0.2 cold_reset:off
Result: G3 -> S0
* Long power press to shutdown:
$ dut-control pwr_button:press sleep:8.2 pwr_button:release
Result: S0 -> S5 -> G3
* Long power press to power-on but then shutdown:
$ dut-control pwr_button:press sleep:8.2 pwr_button:release
Result: G3 -> S0 -> S5 -> G3
* Short power press to power-on:
$ dut-control pwr_button:press sleep:0.2 pwr_button:release
Result: G3 -> S0
* Console command: apreset
Result: S0 -> S5 -> S0
* Console command: power off
Result: S0 -> S5 -> G3
* Console command: power on
Result: G3 -> S0
* Console command: apshutdown
Result: S0 -> S5 -> G3
* Lid open to power-on:
$ dut-control lid_open:no sleep:0.2 lid_open:yes
Result: G3 -> S0
Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969702
We do not want to erase the OCM flash automatically so we
can ensure that we fix our supply chain issues. Add a command
that will erase the OCM if needed.
BRANCH=none
BUG=b:77658388
TEST=verified command works on yorp
Change-Id: Iaf6ada3b1e223d15ae0d9624bdcc54b90cb33b64
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1035428
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds some of the ground work for hardware backed brute force
resistance on Cr50. The feature is called Pinweaver. It will
initially be used to enable PIN authentication on CrOS devices
without reducing the security of the platform. A Merkle tree is
used to validate encrypted metadata used to track login attempts.
The metadata tracks counts of failed attempts, a timestamp of the
last failed attempt, the secrets, and any associated parameters.
Instead of storing the metadata on Cr50 an AES-CTR is used with an
HMAC to encrypt the data so it can be stored off-chip and loaded
when needed.
The Merkle tree is used to track the current state of all the
metadata to prevent replay attacks of previously exported copies.
It is a tree of hashes whose root hash is stored on Cr50, and whose
leaves are the HMACs of the encrypted metadata.
BRANCH=none
BUG=chromium:809730, chromium:809741, chromium:809743, chromium:809747
TEST=cd ~/src/platform/ec && V=1 make run-pinweaver -j
Change-Id: Id10bb49d8ebc5a487dd90c6093bc0f51dadbd124
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/895395
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We need to use the PS8751 as the USB mux without configuring
it as the TCPC. Add mode that allows passing in i2c port
and address instead using tcpc_config_t values.
BRANCH=none
BUG=b:78341944
TEST=build using bip
Change-Id: I45b420ef890dfa8c5e5052864b7a2bb66d8734d6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024486
This change adds a callback for chipset_pre_init_callback which is
made by x86 common power state machine when in G3S5 state. Until now,
there was a hook CHIPSET_PRE_INIT_CALLBACK that was notified by
chipset task when in G3S5 state. However, there are at least following
reasons why this should be a callback and not a hook notification:
1. The initialization that is done as part of pre-init could be
essential for the power state machine to make progress. Though the
chipset task goes to sleep waiting for power signals after the hook
notification, pre-initialization can all be done as part of a callback
since it is mostly board-specific code that is doing work to
initialize PMIC.
2. Typically, boards use I2C transactions to setup PMIC on getting
chipset pre-init notification. However, since i2c transfers are not
encouraged in hook task, they have to be deferred anyways.
3. Since the initialization is being done as part of hook task, use of
any constructs e.g. pwr_5v_en_req which allows multiple consumers to
enable/disable power rails will use task id for hook task. Instead it
is better to provide correct information about the task by letting
chipset task perform this request.
Thus, this change adds a callback chipset_pre_init_callback in G3S5
state for x86 power state machine. This callback is guarded by
CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK.
The hook notification is left as is for now until all x86 boards are
moved over to using the newly added callback.
BUG=b:78259506
BRANCH=None
TEST=None
Change-Id: I2e1d73e5308759fef41680ae715ef71268b61780
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018733
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Now that board version can come from CBI, we can have a real error
reading it. We should pass that error to the console or to the
AP on the host command and let the AP firmware (or user) decided how to
handle that error case
Also update the CONFIG_BOARD_VERSION to be derived instead of needed
in most cases.
BRANCH=none
BUG=b:77972120
TEST=Error reported on EC console and AP console when CBI is
invalid on yorp
Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1015776
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit adds an optional console command that will dump the contents
of the battery charger IC registers. Currently, the only chargers
supported are the BD9995x as well as the ISL923x.
BUG=None
BRANCH=None
TEST=Enable on meowth; Flash; Verify that the command works without any
issues.
Change-Id: I2221efe0ed6e0f6063c97547e0da2d775bf4da45
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1016004
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This CL adds support to check if the OCM flash is erased and if not,
will erase it at initialization time. These changes are encapsulated
in a new config option CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE and this
option is enabled for Yorp boards.
BUG=b:77658388
BRANCH=NONE
TEST=make -j buildall. Tested on a board that hadn't yet been
erased. Verifed the message
"anx7447: OCM flash checked and successfully erased"
was in the EC log, but did not show up on subsequent reboots.
Change-Id: I660e76a9498d3dc1ba821a04317b324f716c5089
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/988414
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
charge_prevent_power_on() had sections which were gated on the following
CONFIG_* option:
CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
However, the block of code that this gated didn't even take the battery
percentage into account and made it very confusing as to why.
This commit simply changes the CONFIG_* option used to gate to be the
following:
CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
This better reflects the checks that were actually being made.
Additionally, this CONFIG_* option is defined by default for boards that
have a chipset task and is initialized to 15W, which is the power that
indicates that the charger is likely to speak USB PD.
BUG=b:76174140
BRANCH=None
TEST=make -j buildall
Change-Id: Ic9158dd7109ce6082c6d00157ff266842363b295
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/977431
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Port 0 uses the Anx7447. This CL updates the tcpc config to use the
Anx7447 driver instead of the Anx74xx driver.
BUG=b:74127309
BRANCH=NONE
TEST=make -j BOARD=yorp and verified that when connected external type
C charger to port 0 it reaches SNK_READY
Change-Id: I96967a1d272fcda079280ba6d2f0eb5ed8e3dd7f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982894
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Use RMA public key definition generated based on the binary blob
containing the key and key ID.
Key generation is controlled by the make file in common/, but actual
key blob comes from the board directory.
The structure holding the key and key ID is being modified to allow
initialization using a flat array.
No more need in defining CONFIG_RMA_AUTH_SERVER_PUBLIC_KEY and
CONFIG_RMA_AUTH_SERVER_KEY_ID.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST='make buildall' still succeeds.
test RMA server generated authentication codes are accepted when
unlocking RMA.
Change-Id: I8ade94de6eb69b3e49bc5b948dbac20e59962acf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The semantics in the EC code base are that CONFIG_INTERNAL_STORAGE
implies eXecute-In-Place semantics (XIP). Add a comment to make that
abundantly clear.
BUG=none
BRANCH=none
TEST=none
Change-Id: I80152eeb41dd35716f4c09ffd1753ae128aa7d2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995956
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is a specific option for it83xx chip and is used to
include EC2I module.
And we won't need it without LPC module enabled, so just
depend on CONFIG_LPC.
BUG=none
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I1aa4a182e94d802dbf9ca19cc4a47ef9542d74a7
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/987674
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We have a growing list of boards in chip/npcx/system.c that are
unable to distinguish a reset from a power-on or a reset-pin type.
Instead of being a temporary issue this is now solidified in the
design on some kabylake boards.
Instead of defining board-specific checks in the chip code this
change adds a config option that the relevant boards can define.
BUG=b:76232539
BRANCH=none
TEST=make -j buildall passes
Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979575
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The keyboards that have an assistant key also move the row that
the refresh key is on from 2 to 3. The row is hardcoded and
used by the early boot key detection code to determine if
boot keys should be honored.
The fallout from not having the right refresh row defined was
not seen on Eve because that board has a different quirk where
it does not distinguish reset-pin vs power-on reset types so
the test in check_boot_keys() was not failing.
BUG=b:76232955
BRANCH=none
TEST=manual testing on Eve board
Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979574
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since all of the uses of CONFIG_USB_PD_TCPM_ANX74XX are actually for
ANX3429, rename the option especially since the ANX7447
driver will not reuse the ANX74XX driver which is being introduced
in CL:956790.
Also adding the CONFIG_USB_PD_TCPM_ANX740X and
CONFIG_USB_PD_TCPM_ANX741X options to advertise which versions of the
ANX chip the anx74xx.c driver applies to.
BRANCH=none
BUG=chromium:824208
TEST=build all
Change-Id: Ib47f4661466e54ff2a0c52d517eb318d3bfd25a2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/973558
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The NX20P3483 is a USB PD and Type C high voltage sink/source combo
switch. This CL adds support for this PPC variant. Unlike the TI
SN5S330, the NX20P3483 does not support VCONN and does not need to be
informed of CC polarity by the TCPM. To account for these differences,
2 new PPC config options are added and the driver for the TI SN5S330
was modified to include these new options.
The SNK/SRC switch mode for the NX20P3483 is controlled by 2 GPIO
signals which may be connected the EC or directly to the TCPC. To
handle both cases, the ppc_chips structure was modified with a flags,
snk_gpio, and src_gpio elements.
BUG=b:74206647
BRANCH=none
TEST=make -j buildall and verified there are no build errors.
Change-Id: Ic4415ab7571b80e7661ea673434eaf4cf1f1fd2d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/966926
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This change adds a new config option CONFIG_I2C_XFER_CALLBACK that
makes i2c_xfer callback into board-provided functions before the start
and after the end of every I2C transaction. This can be used by boards
to implement any I2C device-specific quirks e.g. requiring minimum
bus-free time between every I2C transaction when the slave device
cannot actually do clock stretching.
BUG=b:73147310
BRANCH=None
TEST=make -j buildall
Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/956934
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
