Add common defines in bip before we pull them into baseboard
to ensure that the diff of the move is clean.
BRANCH=none
BUG=none
TEST=bip builds.
Change-Id: I06333f2b1ad5d2d7bd057e5e8cd459199393ce1d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1038897
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of doing I2C traffic in an init hook, move it to a
deferred function to be called outside of INIT_HOOK processing.
(identical to CL:1001474 on eve branch, moved to nautilus board
file)
BUG=b:77336348
BRANCH=poppy
TEST=None
Change-Id: Id9eec4333c6f04141e475b61e5aea7b838dcedf7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1033614
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We do not want to erase the OCM flash automatically so we
can ensure that we fix our supply chain issues. Add a command
that will erase the OCM if needed.
BRANCH=none
BUG=b:77658388
TEST=verified command works on yorp
Change-Id: Iaf6ada3b1e223d15ae0d9624bdcc54b90cb33b64
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1035428
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The fallback certificate is provided when TPM is starting up, but the
proper endorsement certificate seed is not found in the RO space.
Unavailability of the proper endorsement cert would be a major failure
for the device using TPM, and it is not supposed to happen: RO space
is protected. On top of that there is no much point in operating with
the fallback certificate.
Let's drop fallback certificate support from the code, leaving it
possible to conditionally compile in for the remote chance of someone
having to debug TPM related problems on the test board (where H1 does
not have proper cert seed in the RO).
BRANCH=cr50, cr50-mp
BUG=b:65253310
TEST=verified that the code without fallback certificate still boots
fine on the debug board.
Compiling with fallback cert disabled saves 2048 bytes of the
flash space.
Change-Id: Ice8fd4ceef03dd7b3bf170e5cee2908b2a99844a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1031055
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This implements keyboard backlight control for Nami, Vayne, Pantheon,
and Sona. On Sona, GPIOC4 is directly connected to the LED strings.
Thus, we use PWM to control the brightness. On the other variants,
the LED strings are connected to LM3509. Thus, we control the brightness
through I2C.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:76182445,b:78141647
BRANCH=none
TEST=Verify keyboard backlight brightness changes on Nami.
Verify keyboard backlight turns on/off on lid close/open, sleep/suspend.
on Nami. Verify 'kblight' returns x set by 'kblight x' on Sona.
Change-Id: I400ea2bc7a58a3cc57eb959179d2139a99ac176c
Reviewed-on: https://chromium-review.googlesource.com/1022833
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
The new TPM API function works even before TPM Startup was executed,
this would allow CCD to read FWMP even if the AP does not boot up.
CQ-DEPEND=CL:1020725
BRANCH=cr50, cr50-mp
BUG=b:67009375
TEST=verified that FWMP can be read both before and after AP is
booted, and that missing FWMP is also processed properly in both
cases.
Change-Id: I4e57e6211fdb8fa3166f261aa861dba9bab433a1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020785
Reviewed-by: Andrey Pronin <apronin@chromium.org>
When plugging in USB-C power with no battery (or cutoff battery),
the ACOK signal from the ISL9238 charger sometimes has a negative
pulse of up to 175 ms after VBUS increases from 5V to 20V.
The width of the pulse varies from board to board.
Increase CONFIG_EXTPOWER_DEBOUNCE_MS to 200 ms (from default of 30)
to ignore this negative pulse.
If we think we are running with no battery and no AC then we will
set the charger voltage to 2.048V, and therefore lose power.
BUG=b:77455171
BRANCH=none
TEST=Plug power into Grunt with no battery.
Change-Id: I9c0f358985e4c630daef93d61c49b87c2e11a480
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1031563
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Our maximum power is 45W so we don't need to keep this limit. Also we can
drop the TODO since we have a bug to track that work.
BUG=b:69683178
BRANCH=none
TEST=emerge-grunt chromeos-ec
Change-Id: Ie40847e3e88653225dc228563c1ac89cc0970316
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1031115
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w
to npcx7m7wb for better clafiication since it introduced new parameter
"b" for chip generation in the same family series.
In new npcx7 series naming rule, it follows:
Format: NPCX7(M)(N)(G/K/F)(B/C)
param M: 8: 128-pins package, 9: 144-pins package
param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
param G/K/F/W: Google EC depends on specific features.
param B/C: Chip generation in npcx7. (Generation A is ignored. It
follows nameing rule in npcx5.)
The all chip variants of npcx7 used in boards are also listed below:
npcx7m6g - for npcx7 ec without internal flash on npcx_evb.
npcx7m6f - for npcx7 ec with internal flash.
npcx7m6fb - for npcx7 ec with internal flash, enhanced features.
npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV.
BRANCH=none
BUG=none
TEST=No build errors for npcx7 series.
Change-Id: I896ee33209efa5d7157c90515005db5f36318c76
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1025471
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In order to be able to recover from the AP and Cr50 getting out of
sync, this logging functionality gives Cr50 a way to track the
state changes of the merkle tree so that the AP can be updated to
the current state as long as it has a recent enough copy.
This involves packing the important information so it can be stored
efficiently on flash, and adding the necessary messages for the
replay.
CQ-DEPEND=CL:895395,CL:929430
BRANCH=none
BUG=chromium:809729, chromium:809745
TEST=cd ~/src/platform/ec && V=1 make run-weaver_ng -j
Change-Id: I40f98de2c8e9706cccb5b922215699f2132fa121
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/963773
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This adds some of the ground work for hardware backed brute force
resistance on Cr50. The feature is called Pinweaver. It will
initially be used to enable PIN authentication on CrOS devices
without reducing the security of the platform. A Merkle tree is
used to validate encrypted metadata used to track login attempts.
The metadata tracks counts of failed attempts, a timestamp of the
last failed attempt, the secrets, and any associated parameters.
Instead of storing the metadata on Cr50 an AES-CTR is used with an
HMAC to encrypt the data so it can be stored off-chip and loaded
when needed.
The Merkle tree is used to track the current state of all the
metadata to prevent replay attacks of previously exported copies.
It is a tree of hashes whose root hash is stored on Cr50, and whose
leaves are the HMACs of the encrypted metadata.
BRANCH=none
BUG=chromium:809730, chromium:809741, chromium:809743, chromium:809747
TEST=cd ~/src/platform/ec && V=1 make run-pinweaver -j
Change-Id: Id10bb49d8ebc5a487dd90c6093bc0f51dadbd124
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/895395
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Also implement a few remaining usb function for bip
BRANCH=none
BUG=b:75972988,b:76218141,b:74132235,b:78344554
TEST=verified yorp still functions
Change-Id: I201408b5db689ac4a5bcab0011bc38698271b851
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024279
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1.5A is really too low for our bringup tests, increase it to max until we have
a battery driver.
BRANCH=none
BUG=b/74395451
TEST="gpioset EN_PP5000_A 1" should not brownout the system
TEST=Backlight can turn on
TEST=Kernel boots and is stable for swboyd
Change-Id: I789b18304c36f6f68296796c076699af722cb5d6
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024502
Reviewed-by: Wai-Hong Tam <waihong@google.com>
We need to tune the i2c parameters for the nuvoton chip on our yorp board
to be able to operate at 400kHz. Currently we do not need the extra speed
or bandwidth, so we are reverting to a lower speed where the default
timing parameters work well.
BRANCH=none
BUG=b:78554726,b:78225299
TEST=HDMI over TypeC works on yorp
This reverts commit 2e7e6665b1.
Change-Id: Ic4ba1d5ef25661bd6c7f9490450af65b4e1393ad
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1028752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds LED control for Akali. Akali needs to show an irregular
pattern in S3 (On 1 sec off 3 sec). This patch adds 'alternate' mode
support. It allows an LED to extend off period. In alternate mode, an
LED goes through on-off-off-off cycles.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77827579
BRANCH=none
TEST=Verify on Nami.
Change-Id: Ia7541236a6c598173cb94089224ac8c0a3f63a68
Reviewed-on: https://chromium-review.googlesource.com/1024691
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
samus_pd is out of space again (groundhogday.jpg). Remove the `crash`
command. This command is needed for a FAFT test (firmware_ECSharedMem)
and you cannot qualify a firmware without it. However, for samus_pd, we
don't seem to run this test against samus_pd itself, but just samus.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I7e34a1a7a9fcdd36e1d97b1226b66dc3f25213f0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/917012
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Wheatley needs more space (probably to store his book collection
including works of Machiavelli). Therefore, enable
CONFIG_COMMON_GPIO_SHORTNAMES to save space.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: Ia5dc8d36c9ae8dea6272a28677609f229a835f96
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/917011
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Apparently the symbol in the yorp schematic is incorrect for our part.
The PMIC_EN signal on ball H6 is actually GPIO72 -- not GPIOD7. Adjust
the gpio used for PMIC_EN.
Note: GPIO72 needs to be put in gpio mode since it defaults to PWRGD
functionality. However, gpio_pre_init() in chip/npcx/gpio.c enables
gpio functionality by default. If that changes, the board options will
need to change as well.
BUG=b:78352179
TEST=Built. Booted. PMIC_EN goes up and down as expected.
BRANCH=none
Change-Id: I955f9a24e0fbecb0cda1380c237fa44c9a575e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1026375
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The PS8751 is only being used as mux with the option of
being a TCPC is we stuff resistor on the subboard. The
default resistor configuration uses ITE EC as C1 TCPC.
BRANCH=NONE
BUG=b:78341944
TEST=none
Change-Id: I4ccad314fa7eec0d205a155e42e52109cff5811f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024487
Side-band wake was only useful when the lid would go in deep-S3,
where the USB interface is disabled. Since we are using S0ix on
poppy and derivatives, the side band wake is useless, and, in
some rare case, may actually cause issues.
BRANCH=poppy
BUG=b:77828249
TEST=Flash staff, can wake soraka from suspend, or from USB
autosuspend.
Change-Id: I23398a792157b32a5d79505dcffc92aaffd4fec2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1011523
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Enabling the SPI slave interface and the host interface depending on the
detected PCH power state.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71986991
TEST=On Meowth, check that the MCU interrupt is seen on the CPU side and
we can still send host commands.
TEST=On ZerbleBarn, verify that the SPI slave interface is enabled at
startup.
Change-Id: Ie7b22e69178bc7d34be6ab28ab24db82fefd5a02
Reviewed-on: https://chromium-review.googlesource.com/966023
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Previously, the base power was enabled when the base was detected by the
lid. However, we should only power the base when the AP is on since it
just wastes power otherwise. This commit adds a pair of chipset hooks
to kick the state machine on startup and disable it on shutdown.
BUG=None
BRANCH=None
TEST=Flash meowth, attach base with AP off, verify that base power is
not enabled.
TEST=Remove base and attach base, verify that base power is disabled
when removed and enabled when attached.
TEST=Shut AP down, verify that base power is disabled.
TEST=Remove base and attach base, verify that base power remains
disabled.
TEST=Power on AP with base detached, verify that base power remains off.
Change-Id: I4379789987dbe91c72d699c4d184b5c5cc812e5f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1020525
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
the latest schematics have been updated to reflect the I2C bus
numbering used in the chip datasheets. this updates the software to
be consistent with the new datasheets. this is only a renaming
exercise, there are no physical changes to the board.
BUG=b:75070158,b:78309559
BRANCH=none
TEST=it compiles
Change-Id: I16e6741c2e8a1dcc32b814a50ba12739f36fd8cf
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020721
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This patch makes the battery LED blink at 0.5 sec interval in white
when battery error is detected.
This patch also changes the pulse interval resolution from 1 sec to 100
msec. There is no functionality change.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:74940319
BRANCH=none
TEST=Verify pulsing and blinking are not affected. Verify battery LED
blinks as intended on Sona.
Change-Id: I0767a6004861b9f07bc846d2ba5bf0df9067a748
Reviewed-on: https://chromium-review.googlesource.com/1017305
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add CONFIG_MKBP_EVENT and CONFIG_MKBP_USE_HOST_EVENT
to send sensor events to AP.
BUG=b:77342604
BRANCH=none
TEST=view sensors in AIDA64 Android app in ARC++
Change-Id: I3687072903d251bccb2cdf7670b0780a906dd22d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1012457
In order to ensure that all chipset init/shutdown operations happen
within the context of chipset task for APL/GLK:
1. Update chipset_force_shutdown to only set a flag force_shutdown to
indicate that chipset shutdown is requested and wake the chipset task.
2. Make chipset task (within the power state machine) call
internal_chipset_shutdown.
3. Make internal_chipset_shutdown reset force_shutdown flag and make a
callback to weak function chipset_do_shutdown to trigger chipset
shutdown.
BUG=b:78259506
BRANCH=None
TEST=Verified that "apshutdown" on EC console results in chipset
shutdown action being taken within chipset task.
Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1018737
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Now that board version can come from CBI, we can have a real error
reading it. We should pass that error to the console or to the
AP on the host command and let the AP firmware (or user) decided how to
handle that error case
Also update the CONFIG_BOARD_VERSION to be derived instead of needed
in most cases.
BRANCH=none
BUG=b:77972120
TEST=Error reported on EC console and AP console when CBI is
invalid on yorp
Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1015776
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Nami/Vayne uses a dual color LED to show power/charge status as follows:
Charging Amber on (S0/S3/S5)
Charging (full) White on (S0/S3/S5)
Discharge in S0 White on
Discharge in S3/S0ix Pulsing (rising for 2 sec , falling for 2 sec)
Discharge in S5 Off
Battery Error Amber on 1sec off 1sec
Sona - Battery LED (dual color)
AC is attached Solid ON White
charging Solid ON Amber
Discharge in S0 Off
Battery Error Blinking white (0.5 sec On and 0.5 sec Off)
Discharge in S3 Blinking white (1 sec On, 1 sec off regardless AC status)
fuel < 10% Blinking white (1 sec On, 1 sec Off)
Sona - Power LED (single color)
System S0 Soliid On
System S3 1 second on, 1 second off
System S4/S5 Off
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:74940319,b:77941051,b:73999799
BRANCH=none
TEST=Verify LED behaviors in S3, S0, charge, discharge on Nami and Sona
Change-Id: I55b40742135a49f48044f561eb2dbd82b5556d07
Reviewed-on: https://chromium-review.googlesource.com/1011293
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
