We used to have flaky PECI temperature read so we ignored failure. Now
the PECI temperature read seems to work fine so we should have it report
error on failure.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7493
TEST=When powered off, 'temps' shows error on PECI temperature reading.
Change-Id: I161a8f84f66ba06959c21838ee364b2f8d8b4945
This is necessary to support SCI/SMI events.
Note that this breaks compatibility with previous ectool builds - and
probably also breaks flashrom support.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8253
TEST='ectool hello' and 'ectool flashinfo' still work
and 'ectool usbchargemode 3 1' fails with error 2
Change-Id: If39e5b6e7cdcec1b5ec765594e8492925b430b10
Add console command 'autofan' to turn on automatic fan speed control.
Also modify 'fanset' to disable automatic control before setting fan
speed.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manual test
Change-Id: I2db85ce2e754bba21567b2c92e4476049d517627
On the STM32L UART without a FIFO, the Transmit Register might need
some time before pushing its content to the shift register.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on ADV board, verify we are no longer missing most of the carriage
return on console.
Change-Id: Ic638dc452d6e30a5f127710fc964143d477fa1d6
Actual RPM is now read from LPC mapped space. Modify this command to
return target RPM so we can verify EC receives target RPM.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8238
TEST=Get the same value after setting target RPM.
Change-Id: I9bcc9edd327cec1311b51fd0fcbc4a43b353daff
Add a task to update fan speed in LPC mapped memory once per second.
Also added read_mapped_mem16 and read_mapped_mem32.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8183
TEST="ectool pwmgetfanrpm" shows same result as "faninfo" from ec
console.
Change-Id: Ibc536acd39f836ffcad0bfa7c9c14e730220bd49
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I1be67004edb23ccd18ad434c9340bfbecc22e7c4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I8e94c142bf18d07f83bac05287bcd503a098cee7
We now have a task contantly polling temperature sensors, so we need to
use mutex to arbitrate I2C buses.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7491
TEST=temps, i2cscan, and i2cread all work fine.
Change-Id: I1360afb22d98b47da3da0820c95df45c15056f82
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8125
TEST='hibernate 1000' should hibernate and wake back up
Change-Id: I3bf36171ea86a90415593bdc884c004bfff62c4c
The FT4232 chip used on Servo v2 has adaptative clocking feature.
Let's try to use it to avoid signal integrity issue we observe on
Proto-0.5 JTAG.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=connect to Link proto-0 and read/write all the SRAM without errors.
Change-Id: Ic2b91acc29c6d510fb6f3364dd253d3deb650949
A temperature polling task is added to achieve temporal correction and
also reduce the latency of reading temperature.
Factor out sensor specific part to keep code clean.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7801
TEST=On link, 'temps' shows all temperature readings.
Cover each sensor with hand and see object temperature rise.
Compilation succeeded on bds/adv/daisy/discovery.
Change-Id: I3c44c8b2e3ab2aa9ce640d3fc25e7fba56534b86
This loosely ports the LM4 keyboard_scan code to STM32
Notable differences:
- Keyboard GPIO layout is spread across multiple ports and is not
contiguous in many places. Because of this, bitmasks are mostly
generated on-the-fly instead of hard coded (IO is kept to a minimum)
- Longer timeout when scanning columns (100us versus 20us)
Also, some functions are stubbed out currently since they rely on
other bits being implemented:
- keyboard_state_changed()
- keyboard_has_char()
- keyboard_put_char()
BUG=none
TEST=Tested on STM32L-Discovery (monitoring keystrokes via UART)
Change-Id: I84985879589e70688b2b29b288ab17037f7668b2
To accomodate our growing code, image RW.B is removed so that RO and
RW.A can both have 60K space. This is just a temporary solution. Add
RW.B back when we have enough space for all three images.
Also add license header to firmware_image.lds.S so that repo does not
complain about it.
BUG=chrome-os-partner:8079
TEST=build image and run on proto-0.
Change-Id: I85b723f3e645c12fd89b189263ca44d58c4621eb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Compared to Daisy, it has the EC console on USART2 (pins PA2 and PA3)
and regulator enable GPIOS EN_PP1350 and EN_PP5000 are on PA9/PA10.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy && make BOARD=discovery
Change-Id: I545f7c9b05480e58db913ea562c77a1a1cd2b11c
Avoid duplicating in each board file, the stub functions replacing not
implemented drivers on the STM32L platform.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery
Change-Id: I25cd949c31e53a90c39f623617c7d52517a3d205
Allow to set easily the SoC pins to one of their native functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, check the muxing of the USART pins is still
working and we get traces.
Change-Id: I6e83d2eea8986d814720ad4b2fef588908b99079
This CL attempts to abstract underlying bus from i8042 code. Nearly
all i8042 logic is isolated already. This patch is intended to allow
us to use i8042 logic for processing keys and commands on boards which
do not necessarily use LPC as the host <--> KBC bus interface.
This CL does the following:
- Define KBC bus <--> host (kbc_host_bus) on a per-board basis in
board.c.
- Add generic wrappers in place of lpc_keyboard_* in i8042 code.
- Define the behavior of generic wrappers in EC-specific keyboard
sources. If board.c specifies LPC, then send via LPC.
TODO: This needs to be tested on real hardware...
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Locally compiled for Link, BDS and Discovery.
Change-Id: I9cabd514bd44fd6b508c26994eccc3011eedbc0f
Allow to setup edge triggered interrupts on the GPIOs.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=add a adhoc handler for the USER button and check its trace.
Change-Id: I11a280c412c1d333bab4a74f869221edf59fcf8e
This will allow more efficient access to EC-provided data (temperature,
fan, battery) by the main processor.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7857
TEST='ectool hello' from link main processor should still work
Change-Id: I2dc683f3441b34de9fb4debf772e386b9fdcfa82
Implement enable_fpu() and disable_fpu().
enable_fpu() disables interrupt and then enables FPU.
disable_fpu() disables FPU and enables interrupt.
Also added a CONFIG_FPU flag.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: I2d71f396d9c7d7ac4a6a2d525f3d86f8aae87521
Signed-off-by: Vic Yang <victoryang@chromium.org>
This also significantly refactors the module in other ways. Instead
of polling for changes every second, the power button task sleeps
until its next state transition or input.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7508
TEST=manual
1. Reboot EC with lid open. System should NOT power on.
2. Close lid. System should power on.
3. Open lid. System should power on.
4. Press power button. System should power off.
For now, EC debug messages should also indicate [PB task wait] only
when transitions are taking place; the task function should be
sleeping at other times.
Change-Id: I86ac420506cebcdf9ca62bdca342e86857d9e242
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7451
TEST=hold down no keys; KB init state should be blank
hold down reload (F3); KB init should indicate recovery key pressed
hold down F3 + ESC; same
hold down F3 + F2 + ESC; KB init should NOT indicate recovery key pressed
Change-Id: I0fbf15407b20669396f667e6499ee5a9d545a4d5
BUG=chrome-os-partner:7839
TEST=none, work in progress
Change-Id: I20acde8db7f250227adcd4b9dc59328362e68720
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
These provide 8-bit accesses to registers within an I2C device.
BUG=chrome-os-partner:7839
TEST=none
Testing will come when I start using them.
Change-Id: Ib53d3347253bccee93cb9c5da12db92970155d92
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Remove id field from temp_sensor_t struct, since it's only used by the
console command (which already knows the id, because it's looping over
it).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='temps'
Change-Id: I0970850073d644509cd5501d7ac4421c7373143b
We have to wait until the controller is no longer busy before we announce
that we're done. Just waiting for the first interrupt isn't enough, because
that's often just an error indicator and the controller still has to stop.
BUG=none
TEST=none
Change-Id: I065c049111d7de276bf8f7cd0eed39c3f5cff5f4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7493
TEST='powerbtn' to boot main processor, then 'temps' and 'pecitemp'
Change-Id: Id57526ebb37c8aecb05ecebccc2824f462b9de1a
The Daisy board will have the EC UART on the debug connector wired to
USART1 (PA9/PA10 pins)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=Run Discovery board with mini-servo attached to PA9/PA10 and see
the traces.
Change-Id: I97c59ba388fddb150ff6c76ec3317deedb567546
Supports turning system on and off via power button.
Also added 'powerbtn' command, which sends a power button press of the
specified duration, and deprecated the 'x86power s0' command, since
pressing the power button is a more correct way of powering on/off the
system.
Note that current coreboot doesn't seem to boot reliably; when it
fails, the x86 asks for S5 and then S0 a second later. It boots about
every 3rd try. No indication this is due to the EC; the EC just was
ignoring these requests until this CL.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7851
TEST=reboot, 'powerbtn', system should power on
'powerbtn', system should power off
'powerbtn 5000', system should power off regardless of previous state
press power button, system should power on
press power button again, system should power off
hold power button 8 sec, system should power off regardless of previous state
Change-Id: I89f419553289b20c78a57bc8cb1699932b095aa1
Battery charging state machine contains many file changes.
This is the 1st part of the break down. Refactor original
test code into board dummy driver. Normalize charger API.
And import link's charger IC driver.
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7855
TEST=build without warning and error
BOARD=bds make
BOARD=link make
BOARD=discovery make
Change-Id: I34b6e9862a45331378916bc77653d4adb22ca548
Record commands used previously and use up/down arrow key to navigate in
the command history.
Also removed the command '.' of repeating last command as we can use up
arrow key now.
Also changed the behaviour of uart_write_char() to be blocking on
transmit FIFO full, so that we do not lose echoed character and do not
need to flush.
BUG=chrome-os-partner:7815
TEST=Type 'help' and enter. Then type 'aaaa' and up arrow key, should
show 'help', and pressing enter prints help.
Type 'hellp' and enter. Then type 'aaaaaa' and up arrow key, should show
'hellp'. Should be able to use left/right arrow key and backspace to
correct it to 'help', and pressing enter prints help.
Type 'help' and enter. Then type 'aaa', up arrow key, and down arrow
key. Should show 'aaa'.
Change-Id: I65c615d61bf63acb31bea329aa91a3202d4db0ad
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7488
TEST=type things into the x86 console UART; should appear on the u-boot prompt
Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
Refactor board/chip-specific code into corresponding directories.
Add support of the four I2C temp sensor in Link.
Use table lookup to handle different types of temperature sensors.
BUG=chrome-os-partner:7527
TEST=Correctly read EC internal temperature on bds.
Compile for link succeeded.
Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
Original code tests SND bit, but it is not reliable to indicate the
SERIRQ frame has been sent out because the EC always clears it
immediately. Unfortunately the SIRQRIS is always asserted in
continuous mode so that we cannot rely on it.
So, the udelay(4us) method is the best way we can use now.
Note: the quiet mode? Forget it. My EC never sends out further frames
after the first has been sent.
BUG=none
TEST=on bds board.
Change-Id: Ica79b463f3dbe7435fe75f3db4cef00ad7ad5ec0
