For some boards, the control lines to the charging port controller are
all tied to a power rail. In essence, this leaves the ILIM_SEL as the
only signal able to be controlled, which means that we only support
CDP/SDP.
This commit adds a new CONFIG_* option which describes this.
CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
Additionally, some cleanup is made to not always assume the number of
smart power ports.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/634274
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently, chip/g uses jtag_pre_init() to do some chip
pre-initialization that isn't actually related to JTAG. This has been
harmless, but it's currently the only chip which actually does "JTAG"
pre-init, and we'd like to get rid of that. So, move that
functionality to a new optional chip_pre_init() function.
BUG=chromium:747629
BRANCH=cr50
TEST=make buildall
boot cr50
make all dis; confirm chip_pre_init() is called early in <main>
Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/629876
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the board level TCPC run as an init hook it will frequently
lead to an EC reset when we are trying to recovery a disconnected
battery, potentially even a reboot loop with the most unlucky
timing.
If we instead call it from the pd_task before tcpc_init is called
then the board init hook can stall the pd_task init until the
battery is out of disconnect mode, or giving up after 2 seconds
in case the battery never seems to recover.
This accomplishes two goals: ensure the PD chips are not reset until
the battery is out of disconnect and delay start of the pd_task
(and PD negotiation) until the battery is out of disconnect state.
This change was done in the Eve FW branch. Pulling it into TOT so it
can be used for other boards that have the same
issue. https://chromium-review.googlesource.com/c/592716. The change
to wait for the battery to be out of disconnect mode is in the board
specific board_tcpc_init() function and so will be in subsequent board
specific CLs.
BUG=b:63957122
BRANCH=none
TEST=manual Verify that 'make buildall' is successful.
Change-Id: I14c3dbb89cdc05fa9231fbe9db2e1de19fa941b6
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627114
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to satisfy factory testing requirements we need to
boot a bare board with just an AC adapter without requiring
a power button.
However we also don't want to always allow booting of the
battery is present but cut-off (which will indicate BP_NO so
we can't use the existing battery_is_present function) or has
critically low level as it may not immediately boot.
To accomplish this add a function that allows the board to
specify a custom "hardware presence" for the battery that is
separate from the battery presence check.
This CL is taking a change done for Eve and pulling into TOT so it can
be used for other projects that have the same
requirements. https://chromium-review.googlesource.com/c/582544
BUG=b:63957122
BRANCH=none
TEST=manual
Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627113
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this makes the PD_CONTROL_DISABLE subcommand of EC_CMD_PD_CONTROL port
specific like all the other subcommands already are.
the only place depthcharge uses PD_CONTROL_DISABLE is in anx7688.c and
that code already passes the correct chip ID along, so this will not
affect the current use case. ectool already does the right thing as
well.
TEST=used ectool to verify each port can be disabled independently.
BRANCH=none
BUG=b:64956885
Change-Id: I6514eb300793b8958ed78846298ec5b95f78e6dc
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/616259
Reviewed-by: Shawn N <shawnn@chromium.org>
Use the previously introduced TPM logging framework to log TPM reset
events. The two lowest data field bits are used to communicate the
type of reset passed to tpm_reset_request(),
BRANCH=cr50
BUG=b:63760920
TEST=with the upcoming patches verified that TPM initialization is
logged as expected
Change-Id: Ic0874723ec6df616a8237b036542398b29fe5ccc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/620113
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
SVr4/4.3BSD/C89/C99 use a return value of size_t. To
make interaction with code running on both userland
and on the EC easier, change our function prototype
to return size_t as well.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
BUG=none
TEST=make buildall -j works
Change-Id: I0f097c4d0db4232d888e1d54e6c1d22f4859a112
Reviewed-on: https://chromium-review.googlesource.com/618269
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
A common failure condition on the i2c bus is when the master
unexpectedly stops clocking the bus while the slave is driving the SDA
line low. In this case the master is not able to issue Stop or Start
sequences, which makes the bus unusable.
Good slave controllers are able to detect this condition and recover
from it by removing the pull down from the SDA line. This patch adds
this capability to the g chip i2c slave controller.
A new timer function is created which samples the SDA line twice a
second. If it detects that SDA is low in two consecutive invocations
and the number of i2cs read interrupts has not advanced, it decides
that the "hosed slave" condition is happening and reinitializes the
i2c driver, which removes the hold from the SDA line.
Even though the state of the SDA line is supposed to be accessible
through the I2CS_READVAL register, it in fact is not, reads always
return zero in the SDA bit. To work around this a GPIO (port 0, bit
14) is being allocated to allow to monitor the state of the line, it
is multiplexed to the same pin the SDA line uses.
When the AP is in low power modes the SDA line is held low, this state
should not trigger i2c reinitializations.
CQ-DEPEND=CL:616300
BRANCH=none
BUG=b:35648537
TEST=connected H1 on the test board to an I2c master capable of
stopping clocking mid byte. Observed that the existing code would
just sit in the "hosed" state indefinitely. The code with the fix
recovers from the condition (drives the SDA line high) 500ms to
1s after the failure condition is created.
Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/614391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
A subsequent CL will massively refactor the device state machines.
Add the helper functions which will be used by that CL, so that
the refactoring touches fewer files.
No change in functionality.
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50 with a CR50_DEV=1 image
Change-Id: I3499d45e93fa15b6de9c04ce398d1c5bfbbc01e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616300
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This way, when HOOK_CCD_CHANGE triggers, the debug message is printed
before any of the effects of the change due to other hooks.
No effect on the rest of the code.
BUG=none
BRANCH=cr50
TEST=manual in CR50_DEV=1 image
ccdlock
ccdoops
"CCD change hook called" should be seen before "Enabling I2C" or
"Disabling I2C" messages.
Change-Id: I2e083b70fe8ac3938abc56e14b5e50fe9e237752
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616179
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
In the SRC_READY state, we'll only request sink caps if we haven't
received them yet and only if its the first transition to the state.
However, we also don't send any PD traffic in that state if there's an
incoming message in order to prevent a collision. This could create a
scenario where upon entry to the SRC_READY state, a message is incoming.
When this occurs, we never request the sink caps.
This commit simply removes the condition that we may only request sink
caps on the first transition to the SRC_READY state.
BUG=b:64037926
BRANCH=gru
TEST=Flash kevin; Connect to a DR port partner; Verify that sink caps
are requested even after the first transition to the SRC_READY state.
Change-Id: I6bc9ad01d45e6584a7a14b28806ae4872a22d98f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611320
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is defined for a board, as
its name implies, the board can source a higher current if there is
only one port acting as a source.
This commit fixes an issue with selecting the right source capability
message to advertise. charge_manager_get_source_pdo() was simply
checking if there was more than one sink connected, instead of checking
if there were any *other* sinks connected. In the event that a sink
was connected to a different port, we would advertise the max source
PDO.
BUG=b:64037926, b:35577509
BRANCH=gru,eve,reef
TEST=Connect sink to port 1. Connect a AMA to port 0 that claims that
VBUS isn't necessary. Start sending source caps, verify that the max
PDO is not being advertised in the source caps.
Change-Id: Ie4145ecaf98d5b9070ad3e8b139e5653685fa801
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/610479
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow TPM to log events in a circular buffer through tpm_log_event().
Logs can be retrieved through a new vendor command
VENDOR_CC_POP_LOG_ENTRY.
BUG=b:63760920
TEST=On eve, store TPM logs through 'logentry' cr50 console command,
verify logs are fetched correctly through 'trunks_send --pop_logentry'.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idbc405728c0ba68078447fb59717d6115830e3d8
Reviewed-on: https://chromium-review.googlesource.com/599352
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In the field, we want to update touchpad FW using the same USB
update protocol as the main EC FW.
To distinguish between EC FW update and touchpad FW update, we
use a virtual address, defined by CONFIG_TOUCHPAD_VIRTUAL_OFF,
that does not map to anything on the EC chip.
Also, this will allow us to verify hashes of each block of the
flashed touchpad firmware, so that we can ensure its integrity
before flashing it into the touchpad. A stub is implemented in
update_fw.c:contents_allowed.
BRANCH=none
BUG=b:63993173
TEST=With follow-up CLs, ./usb_updater2 -p 144.0_2.0.bin
Change-Id: I4de1d7d138fc01fe1552a4173c8ef208ecb834a7
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/593373
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
If board selects both CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF and
CONFIG_HIBERNATE, then CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF should
be given higher preference when deciding what action to take in case
of critical battery.
This is necessary on boards where components like H1 chip could be
consuming more power than is healthy when the battery is already
critically low, depleting it to dangeriously low voltage levels faster
than it should.
(Reference: https://chromium-review.googlesource.com/582543)
BUG=b:64460667
BRANCH=None
TEST=Manual testing to ensure that EC cuts off battery when it is
critically low instead of hibernating on soraka.
Change-Id: I6efacd7206199ca19f1073296b113b6cf18ec655
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/605014
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This mostly adds a bunch of comments, but does make a few changes to
the code:
1) The devices console command now prints both the current device
state and the last known state.
2) servo_state_unknown() also checks if we're bit-banging the EC UART,
since that could also cause EC_DETECT to go high.
BUG=none
BRANCH=cr50
TEST=make buildall; use 'devices' command
Change-Id: I73e7524545ef49494eb36155b99f4042c1fd466d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/602695
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
In all states other than STATE_NONE, ensure that there is a deferred
call set after DEBUG_TIMEOUT so that debug mode exits if there is no
user activity.
BUG=b:64436180
BRANCH=None
TEST=make -j buildall. Also, verified following:
1. All combos still work fine
2. No user input for 10 seconds after entering debug mode:
++[42.318691 DEBUG MODE: Active!]
++[53.288057 DEBUG MODE: Exit!]
3. No user input for 10 seconds on sysrq path:
++[95.675863 DEBUG MODE: Active!]
+[97.200743 Button 'Volume Down' was pressed]
[97.526162 Button 'Volume Down' was released]
[107.528069 DEBUG MODE: Exit!]
4. No user input for 10 seconds on warm reset path:
+[149.374805 DEBUG MODE: Active!]
[150.863902 Button 'Volume Up' was pressed]
[151.193353 Button 'Volume Up' was released]
[161.199244 DEBUG MODE: Exit!]
5. Volup+Voldn still held down 10 seconds after entering debug mode:
+[213.704770 DEBUG MODE: Active!]
[223.705368 DEBUG MODE: Exit!]
Change-Id: I8a0aa448d31b4a746c7af2519ac6f61838bc9b99
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/603991
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Implement the RFC 6979 to get a deterministic integer k when doing the
ECDSA signing of the x.509 certificates used by U2F and particularly
individual attestation mechanism, rather than using the random generator
as per the original ECDSA algorithm.
So the generated certs have bit-for-bit identical signatures when the
content is identical.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=cr50
BUG=b:35545754
TEST=pass U2FTest and manually dump several individual attestation certs,
run the "rfc6779" console command when enabled.
Change-Id: I7b73eee6d5a863aae9a7eec49db884151bad5ab4
Reviewed-on: https://chromium-review.googlesource.com/558073
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
add a subcommand to the PD_CONTROL message to power up a specific
TCPC. in practice, this typically just takes the TCPC out of sleep
mode for cases where sleep mode is controlled by the EC.
under the covers, board_set_tcpc_power_mode() gets a weak function
definition so we don't need to special case this everywhere.
TEST="make buildall" passes; "make tests" passes for reef.
BRANCH=none
BUG=b:35586895
Change-Id: Ib50e265d11eca10c3714049d8cfdf2657eff48c1
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/596796
Reviewed-by: Shawn N <shawnn@chromium.org>
We'd like to know touchpad vendor/product id, as well as currently
running FW version. This CL does that by adding a new
UPDATE_EXTRA_CMD_TOUCHPAD_INFO command.
We also make the interface more generic by adding a CONFIG_TOUCHPAD
configuration option, even though we only support Elan touchpads
currently.
BRANCH=none
BUG=b:63418037
TEST=Flash hammer, ./usb_updater -t
Change-Id: Icce3c785eb3235bcc50b2ae7c0227ce11cbc9f2b
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/593000
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
Save a small amount of time when the USB resume is making the chip boot
from deep-sleep by removing the verbose serial traces in main and
increasing the usb initialization priority.
This brings us from borderline timings wrt the USB specification to a
reasonable margin.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=run on hotelgolf, go to deep-sleep on USB-suspend.
On USB resume, measure the time from CPU boot to the end of usb_init
using the CPU cycle count. We are shaving 1.3ms.
Change-Id: Ia5bf69c0ca26748dec59a87f3908a5fe68296b36
Reviewed-on: https://chromium-review.googlesource.com/563206
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We can re-use our pd_log FIFO for other purposes, such as TPM logging.
Carve out event_log, a generic logging module which pd_log is compatible
with.
BUG=b:63760920
TEST=On kevin, verify PD logging is still functional and entries are
seen in dmesg.
BRANCH=None
Change-Id: I8e6ad6f93e9eebc676aca64652c60f81da471a94
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/597314
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the chip is used in the factory harness, the AP device state is
set to off, which prevents tpm reset from being invoked, which in turn
prevent the certificate from being copied into NVMEM.
Let's not wait for the AP to be up when running in chip factory mode.
BRANCH=cr50
BUG=b:63686091
TEST=running cert installation procedure produces SPI dummy byte of
c0c0c0c0... after the successful installation and of cbcbcbcb...
after repeated cert installation attempts.
Change-Id: Ibc4ff50511dccd8412a380ec03fc5ff8a14b0282
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/594953
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add usb_i2c_board_is_enabled().
On Cr50, this is now also connected to the I2C CCD capability. The
USB-I2C bridge can only be used when the capability is available.
On other platforms (Servo V4, etc.) where usb_i2c_board_enable() is
a no-op, add a dummy implementation which always returns true.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1
Connect host PC to dev board USB port
On host PC:
sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml
dut-control pp3300_ec_shv_reg --> fail, error 0x8001
ccdoops --> reset I2C config
ccd i2c disable --> I2C disabled
On host PC:
sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml
dut-control pp3300_ec_shv_reg --> fail, error 0x0006
ccd i2c enable --> I2C enabled
ccdunlock --> I2C disabled
ccdoops --> I2C enabled
ccdset i2c unlesslocked
ccdlock --> I2C disabled
ccdunlock --> I2C enabled
Change-Id: Ia3df32e239a5f7c5915bc6c7e408ce0dc8b26c89
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590577
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
When in factory mode, we should not be trying to figure out board
strapping options, just enable SPI interface so that the tester can
communicate with the chip.
Also, to close the loop with the tester, let's add indication of the
cert installation result, by setting the two top bits of the DUMMY
(aka underrun) character to 1 and the lower bits to the endorsement
operation result (0 means success, nonzero values communicate
different failure modes) and by preventing the TPM driver from sending
anything but underrun chars on the SPI interface.
BRANCH=cr50
BUG=b:63686091
TEST=pending
Change-Id: I1a22ed6988ad87dd929a393359c4604e6ecd3b58
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/578651
Reviewed-by: Nick Sanders <nsanders@chromium.org>
One Time Programmable memory can be used to store permanent data like
serial numbers.
Reorganize the code to support writing serial number to OTP, in
addition to pstate (if using its own memory bank) or autogenerate from
unique id (hammer).
+ Add CONFIG_OTP to enable OTP code
+ Add CONFIG_SERIALNO_LEN to indicate the size of the serial number
string. Currently set to 28, when USB serial number is needed.
+ Expose flash_read|write_pstate_serial and add otp_read|write_serail,
remove more generic flash_read|write_serial.
+ Make board_read|write_serial generic, declared outside of USB subsystem.
Priority order to read|write serial string:
- board definition (like hammer)
- pstate location, if stored in its private memory bank
- otp area
If none of these methods are available, a compilation error is raised.
BUG=chromium:746471
BRANCH=none
TEST=compile
Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580289
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Allow host to request a higher-power S3 variant, "wakeable S3", in which
more wakeup sources will be enabled by the EC. The actual implementation
and list of wake sources is left up to the chipset power driver and/or
board code.
BUG=b:63037490
BRANCH=gru
TEST=With subsequent commit, compile on scarlet w/ power sequencing
version = 2.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I469f0cd969052f173cb176196bb6d05f6f76fdb5
Reviewed-on: https://chromium-review.googlesource.com/572210
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
If there is a board ID mismatch and rollback is not possible Cr50
firmware will enter a limited mode which only support Cr50 firmware
upgrade. All other features must be disabled, because it is not
possible to know which features should be allowed on the mismatched
board.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build, define CONFIG_CMD_CCDDISABLE
ccdinfo --> state=opened
ccddisable --> state=locked(disabled), all capabilities disabled
ccdunlock --> access denied
ccdopen --> access denied
ccdreset --> access denied
ccdpassword --> access denied
ccdset --> access denied
ccdoops
ccdinfo --> state=opened, back to defaults
Change-Id: Idb66fb1f3d5106aa0c2cb6addf2404ea9942b0d6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590070
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Define two bits in a long-life register to hold the current CCD state
across deep sleep. Update the bits on CCD config change, and restore
them on init.
This is necessary because Cr50 loses RAM contents on deep sleep. It
would be really inconvenient to open CCD, get a cup of coffee, and
come back to find CCD has locked again because Cr50 was idle too long.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
ccdinfo --> state=opened
idle d
ccdunlock
ccdinfo --> state=unlocked
(wait for deep sleep)
sysinfo --> reset flags = hibernate wake-pin
ccdinfo --> state=unlocked
reboot
sysinfo --> reset flags = hard
ccdinfo --> state=opened
Change-Id: I7864f374af5c159bc9691b094958fb030f3cb8ad
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575996
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
BUG=chromium:736603
BRANCH=none
TEST=Follow the steps below
1) add MAX17055 config to Scarlet and build the code
2) hook up max17055 eval board and a single cell battery
3) battery command from ec console shows reasonable numbers
for temperature, voltage, and charge percentage
Change-Id: I3f838ff92c591665e9f1d0a7ba636ff83d9b7612
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/578300
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some chips require special operations before flash can be accessed
(read, write, erase), without it the flash operations could be
corrupted. The chip that requires this should enable the
CONFIG_FLASH_SELECT_REQUIRED config, which exposes
EC_FLASH_INFO_SELECT_REQUIRED in flashinfo flags. Before any flash
operations is executed on the chip, EC_CMD_FLASH_SELECT should be issued
to notify the chip to prepare for the flash operations.
BRANCH=none
BUG=b:63685022
TEST=with depended CLs, touchpad interrupt should be disabled when
flashrom is in progress.
CQ-DEPEND=CL:*416548
Change-Id: I96455adbe739d5f924edf382a2752404a7c5ad04
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/582374
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Pass in recovery button press/release information to AP using MKBP
button driver.
BUG=b:63893483
BRANCH=None
TEST=Behavior verified by Shelley.
Change-Id: I7a6e50ec8595d99327b5fc8e822bf762e0ce13e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580539
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds the CCD configuration module, and the console commands to
control it. It is not wired up to any of the CCD capabilities; that's
coming in the next CL.
Briefly:
* CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to
print it.
* CCD can be Locked, Unlocked (some capabilities), or Opened
(all capabilities), using the ccdlock / ccdunlock / ccdopen commands.
* CCD config can be restricted by setting a password via ccdpass.
* Individual config capabilities can be set via ccdset. Some of those will
be used to gate access to things like write protect and UARTs. Others
affect the requirements for ccdunlock / ccdopen (for example, is physical
presenc required).
* The entire config can be reset via ccdreset. If only unlocked, config
that is restricted to Opened is not reset.
* If CR50_DEV=1, ccdoops will force-reset and open the config.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual with CR50_DEV=1 build
gpioget # make sure GPIO_BATT_PRES_L=0
ccdlock # lock, because CR50_DEV=1 builds start unlocked
ccdinfo # locked, flags=0, all capabilities default
ccdpass # access denied (we're locked)
ccdreset # access denied
ccdset flashap always # access denied
ccdunlock
ccdinfo # unlocked
ccdpass foo
ccdinfo # flags=2 (password set when unlocked)
ccdset flashap always # access denied
ccdset uartectx unlesslocked
ccdinfo # yes, uartectx permission changed
ccdlock
ccdunlock # fails without password
ccdunlock bar # wrong password
ccdunlock foo # busy
(wait 3 sec)
ccdunlock foo
ccdreset
ccdinfo # no password, flags 0, capabilities all default
ccdopen # requires physical presence; tap power or use 'pp'
ccdset uartectx unlesslocked
ccdset batterybypasspp ifopened
ccdpass baz
ccdinfo # password set, flag 0, ccdset changes worked
ccdunlock
ccdreset
ccdinfo # uartectx back to ifopened, password still set
ccdopen baz # still requires physical presence
ccdset opennolongpp always
ccdlock
ccdopen baz # no pp required
ccdset unlocknoshortpp unlesslocked
ccdlock
ccdopen baz # short pp sequence required (3 taps)
ccdlock
ccdunlock baz # short pp sequence required
ccdopen baz # pp not required
ccdset unlocknoshortpp always
ccdlock
testlab open # access denied
testlab enable # access denied
ccdunlock baz
testlab open # access denied
testlab enable # access denied
ccdopen baz
testlab enable # requires short pp
ccdinfo # flags 1
ccdreset
ccdinfo # no password, flags=1, caps all default
ccdlock
testlab open
ccdinfo # opened
testlab disable # requires short pp; let it time out
ccdinfo # still opened, flags=1
ccdlock
ccdoops # backdoor in CR50_DEV images to force-reset CCD
ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab)
ccdreset rma
ccdinfo # flags = 0x400000, everything but Cr50FullConsole always
ccdreset # back to flags=0, all default
Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9
Reviewed-on: https://chromium-review.googlesource.com/569439
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This will be used as part of case closed debugging configuration.
Currently, this only adds the state machine, and a test command which
is available when CR50_DEV=1. It also adds a new sleep mask flag for
physical presence detect, instead of oveloading FORCE_NO_DSLEEP.
The physical presence state machine supports both short (tap 5 times
in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes
apart) sequences. It will call a callback function at the end of the
sequence, so that multiple things can each request physical presence
in turn. This will be used by ccdopen / ccdunlock / testlab commands
for CCD V1.
Eventually, CCD config will replace the unlock sequence handling in
wp.c. But for now, we don't touch that.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual
Short sequence:
pp short
pp
pp
pp # See "Physical presence good"
Timeout
pp short
pp # 15 sec later, get timeout error
Long sequence:
pp long
pp
pp
pp
(wait 2 sec)
pp
(wait 2 sec)
pp # See "PP good"
Long sequence, presses too fast:
pp long
pp
pp
pp
pp # See "PP L too soon"
(wait 2 sec)
pp
(wait 2 sec)
pp # See "Physical presence good"
Abort:
pp short
pp abort # See "Physical presence aborted"
Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568796
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This patch clears RESET_FLAG_AP_OFF on recovery boot so that the
system boots immediately regardless of the previous power state.
BUG=b:63669512
BRANCH=none
TEST=Verify the followings on reworked Fizz:
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS/PASS
(*1: b:63668669)
Change-Id: If300fc9ec28ff0f7833e84a02e174e501b6a5016
Reviewed-on: https://chromium-review.googlesource.com/570948
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change makes EC run vboot in the HOOK task. The vboot routine
requires battery and charger info. It waits in a deferred call
loop until the charge manager is initialized.
BUG=b:63586051
BRANCH=none
TEST=Verify the following cases:
A. Hardware reboot (type-c/BJ)
1. Unplug AC in S0 then plug in AC: BOOT/BOOT
2. Unplug AC in S5 then plug in AC: S5/S5
3. Unplug AC after A.2 then plug in AC: S5/S5
4. Press PB in S5: BOOT/BOOT
B. Software reboot (type-c/BJ)
1. Run EC reboot command in S0: BOOT/BOOT
2. Run EC reboot command in S5: BOOT/BOOT
3. Run EC reboot ap-off command in S0: S5/S5
4. Run EC reboot ap-off command in S5: S5/S5
5. Run host reboot command: BOOT/BOOT
6. Run host shutdown command: S5/S5
C. Recovery tests
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS(*2)
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2)
*1: b:63668669
*2: b:63669512. Requires one more PB press.
Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568699
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch moves the code which can be shared with other data
verification schemes (e.g. RWSIG) under common/vboot. It also
adds unit tests for it.
BUG=b:38462249
BRANCH=none
TEST=make run-vboot. Verify verification succeeds on Fizz.
Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/563463
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch gives EC the capability of verifying and jumping to
RW_A or RW_B. EC tries the slot stored in a persistent storage
(e.g. BBRAM). If verification fails due to invalid contents, EC
tries the other slot. AP's expectation and its reaction to the
state of the slots and the currently running image are summarized
below.
Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC
won't try to verify or jump to RW yet.
| AP expects X
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X' | reboot to B
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X' | reboot to A
----------+---------------------------
SLOT_A=X' | write X to B, reboot to B
SLOT_B=X' | write X to A, reboot to A
BUG=b:38462249
BRANCH=none
TEST=Lock the system and boot Fizz on barrel-jack and type-c.
Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/556286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit increases the precision used in the noisy magnitude
deviation check by multiplying the scaled sensor data by 8 in the
intermediate calculations. Prior to this, due to some bits being lost,
certain devices would determine the lid angle as unreliable in specific
angles, even though the device was at rest.
BUG=b:63148973
BRANCH=eve,gru,reef
TEST=Flash bob, set DUT on desk, run `while true; do ectool motionsense
lid_angle; sleep 0.1; done`, slowly move the lid from 15 degrees until
~350. Verify that no particular angle results in a unreliable lid angle
reading.
TEST=Run `evtest` and examing cros-ec-buttons, fold screen all the way
back to make tablet mode, shake device for at least 30s. Verify that
there are no spurious transitions of the tablet mode switch.
TEST=Repeat above tests on kevin.
Change-Id: Iff06c1df2dd33c60e26a59183f62f29b71548729
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/567050
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch defines load addresses of regions using macros to increase
readability.
BUG=none
BRANCH=none
TEST=Diff firmware_image.lds before and after the change.
Change-Id: I24a13f4676b194efb748522f03c3134d1568f5ae
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/566940
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
For hammer, we do not want to require finalization in factory, so
we just protect RO whenever WP GPIO is set.
BRANCH=none
BUG=b:63378217
TEST=Enable CONFIG_FLASH_PSTATE_LOCKED, flash hammer,
check with flashinfo that RO protection matches WP status.
Change-Id: I902ee478c00a3c932277d2a7d0622c070654a5eb
Reviewed-on: https://chromium-review.googlesource.com/563217
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
