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In the initial design multi-byte registers were being converted to network byte order and so there was reason to treat 1 byte and 4 byte register reads differently. However, since the conversion to network byte order is not being done, there is no reason to treat these cases differently outside of the number of bytes to read. BRANCH=none BUG=chrome-os-partner:40397 TEST=manual Reboot Reef and verify that TPM is working in coreboot coreboot-coreboot-unknown.9999.fbbcb2d Thu Sep 8 19:41:15 UTC 2016 LPSS I2C bus 2 at 0xfe022000 (400 KHz) tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 5 ms I2C TPM 2:50 (chip type cr50 device-id 0x28) setup_tpm():404: TPM: SetupTPM() succeeded src/lib/tpm2_tlcl.c:179 index 0x1007 return code 0 Change-Id: If74c432136c02d334e0d58d16dc817d7773b0584 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/382688 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly