mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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ab9084fd2a
NPCX5* only has one UART controller, which can be switched
between 2 pads. We keep the default pad for EC console,
however, we allow switching to the alternate pad for short,
infrequent, transactions. Both pads are assumed to use the
same baudrate and other line settings.
When switching pad, we first configure the new pad, then switch
off the old one, to avoid having no pad selected at a given time,
see b/65526215#c26.
Because of the added complexity of npcx_gpio2uart (and the fact
that it uses the global variable "pad" define in uart.c), we
move the implementation to uart.c (npcx_uart2gpio is also moved
for consistency).
When the pad is switched to alternate pad, characters input
and output on the EC console (default pad) would be lost. To
compensate for this, we:
- Switch back to main pad in case of EC panic, so that output
is shown on EC console.
- Immediately abort current alternate pad transaction if a
character is received on the default pad. Note, however,
that the first character will be lost (this can be worked
around by telling user to press enter, and have servod/FAFT
always send 2 blank lines (instead of just one) before
sending a command).
- Inhibit pad switching for 500ms after receiving a character
on default pad. Assuming a reasonable typing speed, this
should allow developers to type console commands relatively
comfortably, while not starving the alternate pad communication
for too long.
The logic above could be simplified significantly by implementing
software flow control (XON/XOFF, see b/67026316).
BRANCH=none
BUG=b:65526215
TEST=While follow-up CL that writes long 1k buffers, the following
works fine:
- type 'uart' in EC console
- Read battery power consumption from servod, which "types" in
the EC console:
while true; do dut-control ppvar_vbat_mw; sleep 1; done
no failure is seen.
TEST=Add this test code in uart_alt_pad_read_write, after the pad
has been switched, and check that panic information is
consistently printed correctly:
{
static int t;
if (t++ > 20)
t = t / ret;
}
Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659458
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
430 lines
11 KiB
C
430 lines
11 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "common.h"
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#include "console.h"
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#include "cpu.h"
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#include "host_command.h"
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#include "panic.h"
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#include "printf.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "util.h"
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#include "watchdog.h"
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/* Whether bus fault is ignored */
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static int bus_fault_ignored;
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/* Panic data goes at the end of RAM. */
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static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
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/* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
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static const uint32_t pstack_addr = (CONFIG_RAM_BASE + CONFIG_RAM_SIZE
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- sizeof(struct panic_data)) & ~7;
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/**
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* Print the name and value of a register
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*
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* This is a convenient helper function for displaying a register value.
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* It shows the register name in a 3 character field, followed by a colon.
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* The register value is regs[index], and this is shown in hex. If regs is
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* NULL, then we display spaces instead.
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*
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* After displaying the value, either a space or \n is displayed depending
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* on the register number, so that (assuming the caller passes all 16
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* registers in sequence) we put 4 values per line like this
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*
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* r0 :0000000b r1 :00000047 r2 :60000000 r3 :200012b5
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* r4 :00000000 r5 :08004e64 r6 :08004e1c r7 :200012a8
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* r8 :08004e64 r9 :00000002 r10:00000000 r11:00000000
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* r12:0000003f sp :200009a0 lr :0800270d pc :0800351a
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*
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* @param regnum Register number to display (0-15)
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* @param regs Pointer to array holding the registers, or NULL
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* @param index Index into array where the register value is present
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*/
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static void print_reg(int regnum, const uint32_t *regs, int index)
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{
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static const char regname[] = "r10r11r12sp lr pc ";
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static char rname[3] = "r ";
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const char *name;
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rname[1] = '0' + regnum;
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name = regnum < 10 ? rname : ®name[(regnum - 10) * 3];
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panic_printf("%c%c%c:", name[0], name[1], name[2]);
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if (regs)
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panic_printf("%08x", regs[index]);
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else
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panic_puts(" ");
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panic_puts((regnum & 3) == 3 ? "\n" : " ");
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}
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/*
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* Returns non-zero if the exception frame was created on the main stack, or
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* zero if it's on the process stack.
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*
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* See B1.5.8 "Exception return behavior" of ARM DDI 0403D for details.
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*/
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static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
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{
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return (exc_return & 0xf) == 1 || (exc_return & 0xf) == 9;
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}
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#ifdef CONFIG_DEBUG_EXCEPTIONS
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/* Names for each of the bits in the mmfs register, starting at bit 0 */
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static const char * const mmfs_name[32] = {
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"Instruction access violation",
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"Data access violation",
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NULL,
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"Unstack from exception violation",
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"Stack from exception violation",
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NULL,
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NULL,
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NULL,
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"Instruction bus error",
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"Precise data bus error",
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"Imprecise data bus error",
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"Unstack from exception bus fault",
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"Stack from exception bus fault",
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NULL,
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NULL,
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NULL,
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"Undefined instructions",
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"Invalid state",
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"Invalid PC",
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"No coprocessor",
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NULL,
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NULL,
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NULL,
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NULL,
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"Unaligned",
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"Divide by 0",
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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};
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/* Names for the first 5 bits in the DFSR */
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static const char * const dfsr_name[] = {
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"Halt request",
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"Breakpoint",
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"Data watchpoint/trace",
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"Vector catch",
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"External debug request",
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};
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/**
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* Helper function to display a separator after the previous item
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*
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* If items have been displayed already, we display a comma separator.
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* In any case, the count of items displayed is incremeneted.
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*
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* @param count Number of items displayed so far (0 for none)
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*/
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static void do_separate(int *count)
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{
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if (*count)
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panic_puts(", ");
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(*count)++;
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}
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/**
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* Show a textual representaton of the fault registers
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*
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* A list of detected faults is shown, with no trailing newline.
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*
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* @param mmfs Value of Memory Manage Fault Status
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* @param hfsr Value of Hard Fault Status
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* @param dfsr Value of Debug Fault Status
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*/
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static void show_fault(uint32_t mmfs, uint32_t hfsr, uint32_t dfsr)
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{
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unsigned int upto;
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int count = 0;
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for (upto = 0; upto < 32; upto++) {
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if ((mmfs & (1 << upto)) && mmfs_name[upto]) {
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do_separate(&count);
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panic_puts(mmfs_name[upto]);
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}
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}
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if (hfsr & CPU_NVIC_HFSR_DEBUGEVT) {
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do_separate(&count);
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panic_puts("Debug event");
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}
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if (hfsr & CPU_NVIC_HFSR_FORCED) {
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do_separate(&count);
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panic_puts("Forced hard fault");
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}
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if (hfsr & CPU_NVIC_HFSR_VECTTBL) {
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do_separate(&count);
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panic_puts("Vector table bus fault");
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}
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for (upto = 0; upto < 5; upto++) {
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if ((dfsr & (1 << upto))) {
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do_separate(&count);
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panic_puts(dfsr_name[upto]);
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}
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}
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}
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/*
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* Returns the size of the exception frame.
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*
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* See B1.5.7 "Stack alignment on exception entry" of ARM DDI 0403D for details.
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* In short, the exception frame size can be either 0x20, 0x24, 0x68, or 0x6c
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* depending on FPU context and padding for 8-byte alignment.
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*/
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static uint32_t get_exception_frame_size(const struct panic_data *pdata)
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{
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uint32_t frame_size = 0;
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/* base exception frame */
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frame_size += 8 * sizeof(uint32_t);
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/* CPU uses xPSR[9] to indicate whether it padded the stack for
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* alignment or not. */
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if (pdata->cm.frame[7] & (1 << 9))
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frame_size += sizeof(uint32_t);
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#ifdef CONFIG_FPU
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/* CPU uses EXC_RETURN[4] to indicate whether it stored extended
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* frame for FPU or not. */
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if (!(pdata->cm.regs[11] & (1 << 4)))
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frame_size += 18 * sizeof(uint32_t);
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#endif
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return frame_size;
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}
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/*
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* Returns the position of the process stack before the exception frame.
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* It computes the size of the exception frame and adds it to psp.
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* If the exception happened in the exception context, it returns psp as is.
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*/
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static uint32_t get_process_stack_position(const struct panic_data *pdata)
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{
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uint32_t psp = pdata->cm.regs[0];
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if (!is_frame_in_handler_stack(pdata->cm.regs[11]))
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psp += get_exception_frame_size(pdata);
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return psp;
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}
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/*
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* Show extra information that might be useful to understand a panic()
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*
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* We show fault register information, including the fault address registers
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* if valid.
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*/
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static void panic_show_extra(const struct panic_data *pdata)
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{
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show_fault(pdata->cm.mmfs, pdata->cm.hfsr, pdata->cm.dfsr);
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if (pdata->cm.mmfs & CPU_NVIC_MMFS_BFARVALID)
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panic_printf(", bfar = %x", pdata->cm.bfar);
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if (pdata->cm.mmfs & CPU_NVIC_MMFS_MFARVALID)
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panic_printf(", mfar = %x", pdata->cm.mfar);
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panic_printf("\nmmfs = %x, ", pdata->cm.mmfs);
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panic_printf("shcsr = %x, ", pdata->cm.shcsr);
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panic_printf("hfsr = %x, ", pdata->cm.hfsr);
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panic_printf("dfsr = %x\n", pdata->cm.dfsr);
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}
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/*
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* Prints process stack contents stored above the exception frame.
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*/
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static void panic_show_process_stack(const struct panic_data *pdata)
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{
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panic_printf("\n=========== Process Stack Contents ===========");
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if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID) {
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uint32_t psp = get_process_stack_position(pdata);
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int i;
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for (i = 0; i < 16; i++) {
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if (psp + sizeof(uint32_t) >
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CONFIG_RAM_BASE + CONFIG_RAM_SIZE)
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break;
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if (i % 4 == 0)
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panic_printf("\n%08x:", psp);
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panic_printf(" %08x", *(uint32_t *)psp);
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psp += sizeof(uint32_t);
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}
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} else {
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panic_printf("\nBad psp");
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}
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}
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#endif /* CONFIG_DEBUG_EXCEPTIONS */
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/*
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* Print panic data
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*/
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void panic_data_print(const struct panic_data *pdata)
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{
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const uint32_t *lregs = pdata->cm.regs;
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const uint32_t *sregs = NULL;
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const int32_t in_handler =
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is_frame_in_handler_stack(pdata->cm.regs[11]);
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int i;
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if (pdata->flags & PANIC_DATA_FLAG_FRAME_VALID)
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sregs = pdata->cm.frame;
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panic_printf("\n=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
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in_handler ? "HANDLER" : "PROCESS",
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lregs[1] & 0xff, sregs ? sregs[7] : -1);
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for (i = 0; i < 4; i++)
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print_reg(i, sregs, i);
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for (i = 4; i < 10; i++)
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print_reg(i, lregs, i - 1);
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print_reg(10, lregs, 9);
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print_reg(11, lregs, 10);
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print_reg(12, sregs, 4);
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print_reg(13, lregs, in_handler ? 2 : 0);
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print_reg(14, sregs, 5);
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print_reg(15, sregs, 6);
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#ifdef CONFIG_DEBUG_EXCEPTIONS
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panic_show_extra(pdata);
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#endif
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}
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void __keep report_panic(void)
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{
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struct panic_data *pdata = pdata_ptr;
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uint32_t sp;
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pdata->magic = PANIC_DATA_MAGIC;
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pdata->struct_size = sizeof(*pdata);
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pdata->struct_version = 2;
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pdata->arch = PANIC_ARCH_CORTEX_M;
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pdata->flags = 0;
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pdata->reserved = 0;
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/* Choose the right sp (psp or msp) based on EXC_RETURN value */
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sp = is_frame_in_handler_stack(pdata->cm.regs[11])
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? pdata->cm.regs[2] : pdata->cm.regs[0];
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/* If stack is valid, copy exception frame to pdata */
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if ((sp & 3) == 0 &&
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sp >= CONFIG_RAM_BASE &&
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sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
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const uint32_t *sregs = (const uint32_t *)sp;
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int i;
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for (i = 0; i < 8; i++)
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pdata->cm.frame[i] = sregs[i];
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pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID;
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}
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/* Save extra information */
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pdata->cm.mmfs = CPU_NVIC_MMFS;
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pdata->cm.bfar = CPU_NVIC_BFAR;
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pdata->cm.mfar = CPU_NVIC_MFAR;
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pdata->cm.shcsr = CPU_NVIC_SHCSR;
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pdata->cm.hfsr = CPU_NVIC_HFSR;
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pdata->cm.dfsr = CPU_NVIC_DFSR;
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#ifdef CONFIG_UART_PAD_SWITCH
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uart_reset_default_pad_panic();
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#endif
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panic_data_print(pdata);
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#ifdef CONFIG_DEBUG_EXCEPTIONS
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panic_show_process_stack(pdata);
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/*
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* TODO(crosbug.com/p/23760): Dump main stack contents as well if the
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* exception happened in a handler's context.
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*/
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#endif
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panic_reboot();
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}
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/**
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* Default exception handler, which reports a panic.
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*
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* Declare this as a naked call so we can extract raw LR and IPSR values.
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*/
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void __keep exception_panic(void) __attribute__((naked));
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void exception_panic(void)
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{
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/* Save registers and branch directly to panic handler */
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asm volatile(
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"mov r0, %[pregs]\n"
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"mrs r1, psp\n"
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"mrs r2, ipsr\n"
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"mov r3, sp\n"
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"stmia r0, {r1-r11, lr}\n"
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"mov sp, %[pstack]\n"
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"bl report_panic\n" : :
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[pregs] "r" (pdata_ptr->cm.regs),
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[pstack] "r" (pstack_addr) :
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/* Constraints protecting these from being clobbered.
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* Gcc should be using r0 & r12 for pregs and pstack. */
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"r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
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"r10", "r11", "cc", "memory"
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);
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}
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#ifdef CONFIG_SOFTWARE_PANIC
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void software_panic(uint32_t reason, uint32_t info)
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{
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__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
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"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
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"bl exception_panic\n"
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: : "r"(info), "r"(reason));
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}
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void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
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{
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uint32_t *lregs = pdata_ptr->cm.regs;
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/* Setup panic data structure */
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memset(pdata_ptr, 0, sizeof(*pdata_ptr));
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pdata_ptr->magic = PANIC_DATA_MAGIC;
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pdata_ptr->struct_size = sizeof(*pdata_ptr);
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pdata_ptr->struct_version = 2;
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pdata_ptr->arch = PANIC_ARCH_CORTEX_M;
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/* Log panic cause */
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lregs[1] = exception;
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lregs[3] = reason;
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lregs[4] = info;
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}
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void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
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{
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uint32_t *lregs = pdata_ptr->cm.regs;
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if (pdata_ptr->magic == PANIC_DATA_MAGIC &&
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pdata_ptr->struct_version == 2) {
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*exception = lregs[1];
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*reason = lregs[3];
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*info = lregs[4];
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} else {
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*exception = *reason = *info = 0;
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}
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}
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#endif
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void bus_fault_handler(void)
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{
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if (!bus_fault_ignored)
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exception_panic();
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}
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void ignore_bus_fault(int ignored)
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{
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bus_fault_ignored = ignored;
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}
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