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9a465855f8
Preparatory work to introduce a second SoC : 5/5 All Cortex-M3/4 have the same NVIC registers at the same address. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
24 lines
729 B
C
24 lines
729 B
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and defintions for Cortex-MLM4x processor
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*/
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#ifndef __CPU_H
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#define __CPU_H
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#include <stdint.h>
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/* Macro to access 32-bit registers */
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#define CPUREG(addr) (*(volatile uint32_t*)(addr))
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/* Nested Vectored Interrupt Controller */
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#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
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#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
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#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
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#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
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#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
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#endif /* __CPU_H */
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