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2ea7b194d9
1. To enable INT_PRI (hardware interrupt priority level 0~3) register, bit0@INT_CTRL = 0. 2. GIE need to be enabled before UART is initialized. [symptom] To define CONFIG_RWSIG / CONFIG_RSA / CONFIG_SHA256, then power on: after RW image is verified, firmware stuck in uart_flush_output(). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. bit0@INT_CTRL = 0. 2. The RW image is verified and jump to image RW. Change-Id: I393a3d5f87ea257885b872c91bfce43aecbaea8b Reviewed-on: https://chromium-review.googlesource.com/309400 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
25 lines
627 B
C
25 lines
627 B
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Set up the N8 core
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*/
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#include "cpu.h"
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#include "registers.h"
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void cpu_init(void)
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{
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/* DLM initialization is done in init.S */
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uint32_t image_type = (uint32_t)cpu_init;
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/* To change interrupt vector base if at RW image */
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if (image_type > CONFIG_RW_MEM_OFF)
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/* Interrupt Vector Table Base Address, in 64k Byte unit */
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IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
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/* Global interrupt enable */
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asm volatile ("setgie.e");
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}
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