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nds32: fix interrupt

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1. To enable INT_PRI (hardware interrupt priority level 0~3)
   register, bit0@INT_CTRL = 0.
2. GIE need to be enabled before UART is initialized.
   [symptom]
   To define CONFIG_RWSIG / CONFIG_RSA / CONFIG_SHA256, then power on:
   after RW image is verified, firmware stuck in uart_flush_output().

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=1. bit0@INT_CTRL = 0.
     2. The RW image is verified and jump to image RW.

Change-Id: I393a3d5f87ea257885b872c91bfce43aecbaea8b
Reviewed-on: https://chromium-review.googlesource.com/309400
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Dino Li
2015-10-28 21:39:54 +08:00
committed by chrome-bot
parent ba63ef190e
commit 2ea7b194d9
2 changed files with 22 additions and 0 deletions
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3
core/nds32/cpu.c
View File

@@ -18,4 +18,7 @@ void cpu_init(void)
if (image_type > CONFIG_RW_MEM_OFF)
/* Interrupt Vector Table Base Address, in 64k Byte unit */
IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
/* Global interrupt enable */
asm volatile ("setgie.e");
}

19
core/nds32/task.c
View File

@@ -494,6 +494,19 @@ static void set_int_priority(uint32_t val)
asm volatile ("mtsr %0, $INT_PRI" : : "r"(val));
}
uint32_t get_int_ctrl(void)
{
uint32_t ret;
asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret));
return ret;
}
void set_int_ctrl(uint32_t val)
{
asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val));
}
void task_enable_all_tasks(void)
{
/* Mark all tasks are ready to run. */
@@ -549,6 +562,12 @@ static void ivic_init_irqs(void)
/* chip-specific interrupt controller initialization */
chip_init_irqs();
/*
* bit0 @ INT_CTRL = 0,
* Interrupts still keep programmable priority level.
*/
set_int_ctrl((get_int_ctrl() & ~(1 << 0)));
/*
* Re-enable global interrupts in case they're disabled. On a reboot,
* they're already enabled; if we've jumped here from another image,