The Silego chip has a 50k pulldown which will leak power if we leave
EC_ENTERING_RW high. We don't need to leave it high, because once the
latch in the Silego gets set it ignores this signal. This is ~100uA,
so it only really matters in S5 on pit (since x86 boards and spring
both hibernate in S5).
BUG=chrome-os-partner:20757
BRANCH=none
TEST=probe ec_in_rw signal before/after sysjump
Change-Id: Ib6b09cfc7718b35e4e93c952c3098c08d53572e2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62133
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
245275f4b6