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Cr50 was not waking up long enough after SPS_CS_L was asserted for the spi slave transactions to start and disable sleep. It also was not handling SYS_RST_L properly when it was asleep. This change sets SPS_CS_L to be an edge triggered wake up source instead of level triggered, because cr50 should just wake up on the edge and disable sleep until the spi transaction is done. It also adds sys_rst_l as a wakeup source. The sys_rst_asserted interrupt cannot be triggered while cr50 is asleep, so the pmu_wakeup_interrupt will call sys_rst_asserted if SYS_RST_L is low at resume. This change relies on the EC extending the delay in chipset_reset to be long enough for SYS_RST_L to still be asserted when cr50 resumes. BUG=chrome-os-partner:54331 BRANCH=none TEST=manual make sure suzyq is disconnected. verify ap boots up to the kernel after running 'gpioset SYS_RST_L 0' then 'gpioset SYS_RST_L 1' on the ec console. Check that cr50 goes to sleep when the AP is not trying to use the TPM. When cr50 is asleep pwrbtn + refresh still resets the system. Disable SYS_RST_L_IN as a wake source and verify the system verification fails and requests a recovery image. Change-Id: I807b1918842d96c9d2922aa33404d87ab28b9906 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363606 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly