Vijay Hiremath 3bd4e0de5e Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L ...

Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j

Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

2018-03-24 07:32:29 -07:00

..

g

g: make fw upgrade less chatty

2018-02-26 19:28:55 -08:00

host

test: store persistence files in RAM

2018-01-31 05:58:03 -08:00

ish

ish i2c: use i2c_ports[] to set bus speed

2017-12-13 00:32:23 -08:00

it83xx

Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L

2018-03-24 07:32:29 -07:00

lm4

host_events: Bump up host events and masks to 64-bit

2017-11-21 18:53:35 -08:00

mchp

chip/mchp: Default SPI image script verobse output to disabled

2018-02-09 19:03:26 -08:00

mec1322

system: Allow hibernate to clear AP_OFF flag

2017-12-05 18:00:38 -08:00

npcx

i2c(npcx): Replace cprints by cputs/cprintf

2018-03-17 05:27:48 -07:00

nrf51

cleanup: Remove jtag_pre_init()

2017-09-07 15:01:05 -07:00

stm32

servo_micro: switch parity to 8 bit data

2018-03-12 15:24:39 -07:00