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The high FET on the TX path should be driven low to disable it by default. The SCK pin (SPI clock input for TX) is on PA5. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28337 TEST=scope outputs Change-Id: I72fa52a170ae0e4043beb88d4fd82680ed4aefa2 Reviewed-on: https://chromium-review.googlesource.com/204165 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>