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Since the pending bit of host access interrupt is set frequently if PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering S0. It's better to add checking enable bit of MIWU of it in case huge latency between gpio interrupt and serving its own ISR in INT11's ISR. Modified sources: 1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/352362 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>