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Two accelerometer changes: - Lower accel sampling rate when chipset is off to 10Hz. Increase sampling rate back up to 100Hz when transitioning to S0. - Change the default output data rate of the accelerometers to 100Hz which matches the EC sampling rate when in S0. BUG=none BRANCH=rambi TEST=manual testing. used lidangle command to verify that in S0, EC is sampling at 100Hz, and in S3 or lower it is sampling at 10Hz. Change-Id: Ie4e20f45f9371d674c3325a362d2729c331fac4f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190032 Reviewed-by: Randall Spangler <rspangler@chromium.org>
In the most general case, the flash layout looks something like this: +---------------------+ | Reserved for EC use | +---------------------+ +---------------------+ | Vblock B | +---------------------+ | RW firmware B | +---------------------+ +---------------------+ | Vblock A | +---------------------+ | RW firmware A | +---------------------+ +---------------------+ | FMAP | +---------------------+ | Public root key | +---------------------+ | Read-only firmware | +---------------------+ BIOS firmware (and kernel) put the vblock info at the start of each image where it's easy to find. The Blizzard EC expects the firmware vector table to come first, so we have to put the vblock at the end. This means we have to know where to look for it, but that's built into the FMAP and the RO firmware anyway, so that's not an issue. The RO firmware doesn't need a vblock of course, but it does need some reserved space for vboot-related things. Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If we reserve 4K at the top of each FW image, that should give us plenty of room for vboot-related stuff.