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After sending a hard reset through Control3 SEND_HARD_RESET, packet Tx will fail until PD_RESET is triggered. Therefore, always do such a reset when we see an M_HARDSENT interrupt. Previously, it may have been possible to skip our reset depending on prior Tx packet status, leaving the TCPC in a wedged state. BUG=chrome-os-partner:58232 TEST=Manual on kevin, spam 'pd 0 hard' for 10 hours with zinger attached, verify TCPC is still responsive and negotiating to 20V. BRANCH=gru. Change-Id: I42db792a5f51218c58235dc38c2d49795b54986e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/393769 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 811534541c263244d2fe9bdf9465de196e1575da) Reviewed-on: https://chromium-review.googlesource.com/415486 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly