Anton Staaf fba4f335a9 cortex-m0: Constrain target register in atomic read ...

One more register constaint needed to be added to the cortex-m0 atomic
inline assembly.  Vincent fixed all the others.  The requirement for
ARMv6-m includes that the target load register be one of the low
registers as well.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e
Reviewed-on: https://chromium-review.googlesource.com/292435
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>

2015-08-11 19:52:40 +00:00

..

cortex-m

cortex-m: catch misconfigured interrupts early

2015-08-11 00:06:18 +00:00

cortex-m0

cortex-m0: Constrain target register in atomic read

2015-08-11 19:52:40 +00:00

host

Atomic: Mark the modified uint32_t volatile

2015-07-27 19:30:44 +00:00

nds32

Atomic: Mark the modified uint32_t volatile

2015-07-27 19:30:44 +00:00