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cortex-m0: Constrain target register in atomic read

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One more register constaint needed to be added to the cortex-m0 atomic
inline assembly.  Vincent fixed all the others.  The requirement for
ARMv6-m includes that the target load register be one of the low
registers as well.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e
Reviewed-on: https://chromium-review.googlesource.com/292435
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
This commit is contained in:
Anton Staaf
2015-08-10 14:49:34 -07:00
committed by ChromeOS Commit Bot
parent 3cbc31aec3
commit fba4f335a9
1 changed files with 1 additions and 1 deletions
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2
core/cortex-m0/atomic.h
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@@ -56,7 +56,7 @@ static inline uint32_t atomic_read_clear(uint32_t volatile *addr)
" ldr %0, [%1]\n"
" str %2, [%1]\n"
" cpsie i\n"
: "=&r" (ret)
: "=&b" (ret)
: "b" (addr), "r" (0) : "cc");
return ret;