Vincent Palatin 75b2bcf9b4 stm32l: add timer support
As the STM32L doesn't have any 32-bit timer, we use 2 chained 16-bit
counters to emulate a 32-bit one :
 * TIM2 is the MSB half-word (Slave timer)
 * TIM3 is the LSB half-word (Master time)

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=run timer_calib and timer_dos on the Discovery board, and check
waitms and gettime console functions against wall clock.

Change-Id: I8917207384d967fd87321797856e3d58b237f837
2012-02-01 22:49:22 +00:00
2012-01-31 22:29:13 +00:00
2012-02-01 22:49:22 +00:00
2012-01-31 22:29:13 +00:00
2012-01-25 18:23:48 +00:00
2011-12-07 19:10:02 +00:00
2011-12-08 19:18:06 +00:00
2011-10-20 15:15:01 +08:00

- EC Lib

This wraps Blizzard driverlib and implements the EC chip interface defined
by Google. See below diagram for architecture.


  +--------------------+
  |   Host BIOS/OS     |
  +--------------------+

 ---- host interface ----

  +--------------------+
  | Google EC features |
  +--------------------+

 ---- chip interface ----  The interface is defined in
                           src/platform/ec/chip_interface/*.
  +--------------------+   But the real implementation is in EC Lib.
  |       EC Lib       |
  +--------------------+
  | Blizzard low level |
  |   driver, the      |
  |   driverlib.       |
  +--------------------+

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