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We should clear STASTR to release SCL only after NACK/STOP bits are set. If an interrupt which priority is higher than i2c's issues at this moment, i2c hardware might not generate NACK since SCL is already released by clearing stall's pending bit. Modified sources: 1. i2c.c: Fixed bug i2c sometime cannot generate NACK during Read Byte. BRANCH=none BUG=chrome-os-partner:34346,chrome-os-partner:57452 TEST=make buildall; passed "while(1); do; ectool i2cread 8 0 0x50 0x44; done;" on reef. Change-Id: I68ee5bf3d703cbe4fceefcfcc9afab9cb14bc2dc Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/386586 Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly