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7e8d739b38
The problem comes from the different assumption of interrupt mode in EC and the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge. However, the auto-IRQ functino of EC is level-triggered and uses low-active to assert an IRQ. This makes the deadlock so that the kernel never gets an interrupt until a byte is manually pulled from host. So, the solution is manually firing an IRQ_1 to host after EC puts a byte to port 0x60. Note that the auto IRQ needs to be disabled in order to avoid the interference with manual IRQ generation. This CL also moves chip specific code to lm4/lpc.c and handle some minor keyboard commands. BUG=none TEST=on hacked baord. Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
- EC Lib
This wraps Blizzard driverlib and implements the EC chip interface defined
by Google. See below diagram for architecture.
+--------------------+
| Host BIOS/OS |
+--------------------+
---- host interface ----
+--------------------+
| Google EC features |
+--------------------+
---- chip interface ---- The interface is defined in
src/platform/ec/chip_interface/*.
+--------------------+ But the real implementation is in EC Lib.
| EC Lib |
+--------------------+
| Blizzard low level |
| driver, the |
| driverlib. |
+--------------------+