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Example output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): 00000000
PartNumber(20): HMAA51S6AMR6N-UH
CBMEM_ID_MEMINFO:
dimm_size: 0
ddr_type: 0x1a
ddr_frequency: 1200
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x1a
bus_width: 64
serial(4): 0000
module_part_number(23): HMAA51S6AMR6N-UH ��@
dimm_size, mod_type, bus_width need to be updated so they return the
correct values. module_part_number is missing a null terminator due to
the AGESA part number being larger than the dimm_info buffer.
Example dmidecode output:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 8 bits
Data Width: 8 bits
Size: No Module Installed
Form Factor: Unknown
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 1200 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 0000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 1200 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
To enable the output set CONFIG_DEBUG_RAM_SETUP.
The Kconfig change is required in order to enable
CONFIG_DEBUG_RAM_SETUP, otherwise it's not a valid option.
BUG=b:65403853
TEST=Test output shown above
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eac00b9400056357915761287770a400b3f9f8b
Reviewed-on: https://review.coreboot.org/25303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See https://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * https://www.coreboot.org/Supported_Motherboards * https://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * make * gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case). * iasl (for targets with ACPI support) * pkg-config * libssl-dev (openssl) Optional: * doxygen (for generating/viewing documentation) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig' and 'make nconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult https://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see https://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: https://www.coreboot.org You can contact us directly on the coreboot mailing list: https://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.