Bill Richardson 9b815745fa Cr50: Lower all runlevel permissions to medium ...

Two permission registers are already lowered. This adds the
remaining two.

BUG=chrome-os-partner:52994
BRANCH=none
TEST=make buildall; run on Cr50

USB works, SPI works, sleep and deep sleep work, tpmtest.py works.

Change-Id: Ifb27d5be81f10537114f4702addb58c6d7e1630c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342455
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>

2016-05-05 15:10:24 -07:00

..

tpm2

CR50: fix issue in ecc parameter endian conversion

2016-05-03 15:40:43 -07:00

board.c

Cr50: Lower all runlevel permissions to medium

2016-05-05 15:10:24 -07:00

board.h

cr50: add basic rbox support

2016-04-29 16:07:13 -07:00

build.mk

CR50: add support for P256-ECIES (hybrid encryption)

2016-04-19 22:47:36 -07:00

ec.tasklist

Cr50: Remove HOSTCMD task

2016-04-15 21:29:25 -07:00

gpio.inc

cr50: set SYS_RST_L as an input

2016-04-29 11:02:03 -07:00

Makefile

Add initial support for cr50 SoC

2014-10-31 22:32:50 +00:00

rdd.c

Cr50: Move board-specific rdd stuff out of chip/g/

2016-04-29 07:34:53 -07:00