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Cr50: Lower all runlevel permissions to medium

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Two permission registers are already lowered. This adds the
remaining two.

BUG=chrome-os-partner:52994
BRANCH=none
TEST=make buildall; run on Cr50

USB works, SPI works, sleep and deep sleep work, tpmtest.py works.

Change-Id: Ifb27d5be81f10537114f4702addb58c6d7e1630c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342455
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This commit is contained in:
Bill Richardson
2016-05-02 09:43:46 -07:00
committed by chrome-bot
parent b803590c27
commit 9b815745fa
1 changed files with 8 additions and 0 deletions
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8
board/cr50/board.c
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@@ -69,8 +69,16 @@ enum permission_level {
static void init_runlevel(const enum permission_level desired_level)
{
volatile uint32_t *const reg_addrs[] = {
/* CPU's use of the system peripheral bus */
GREG32_ADDR(GLOBALSEC, CPU0_S_PERMISSION),
/* CPU's use of the system bus via the debug access port */
GREG32_ADDR(GLOBALSEC, CPU0_S_DAP_PERMISSION),
/* DMA's use of the system peripheral bus */
GREG32_ADDR(GLOBALSEC, DDMA0_PERMISSION),
/* Current software level affects which (if any) scratch
* registers can be used for a warm boot hardware-verified
* jump. */
GREG32_ADDR(GLOBALSEC, SOFTWARE_LVL),
};
int i;