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a0119238c7e398135c2b8e4fbb06ba81d4a6a494
- Wait for SLP_SUS to deassert before bringing up PP1050 to avoid leakage when PP1050 is enabled before the PCH is ready. - CPU PGOOD is now connected to RSMRST_L on PCH. Configure this GPIO as an output and hook it into the power sequencing. - Add a "chipset_force_g3()" function to use for aborting G3->S5 transitions when there is an issue with a rail not coming up. BUG=chrome-os-partner:29502 BRANCH=samus TEST=build for samus, tested on reworked p1.9 board Change-Id: Ib0251943864594ee89a4a9f2c71c45da2c01f44e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/203081 Reviewed-by: Alec Berg <alecaberg@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit
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