Duncan Laurie a0119238c7 samus: Power sequence changes for P2 boards
- Wait for SLP_SUS to deassert before bringing up PP1050 to avoid
leakage when PP1050 is enabled before the PCH is ready.
- CPU PGOOD is now connected to RSMRST_L on PCH.  Configure this
GPIO as an output and hook it into the power sequencing.
- Add a "chipset_force_g3()" function to use for aborting G3->S5
transitions when there is an issue with a rail not coming up.

BUG=chrome-os-partner:29502
BRANCH=samus
TEST=build for samus, tested on reworked p1.9 board

Change-Id: Ib0251943864594ee89a4a9f2c71c45da2c01f44e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203081
Reviewed-by: Alec Berg <alecaberg@chromium.org>
2014-06-13 20:37:26 +00:00
2014-05-21 20:32:17 +00:00
2014-06-05 23:14:34 +00:00
2014-03-31 22:45:09 +00:00
2012-05-11 09:11:52 -07:00
2013-12-19 00:12:24 +00:00
2014-04-02 19:58:53 +00:00
2014-05-15 05:20:14 +00:00

For an overview of the Embedded Controller firmware, refer to

http://www.chromium.org/chromium-os/2014-firmware-summit
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