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a48945568e
During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs simultaneously since EC's power rail is turned off by PMIC for a while. VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery mode detection. The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset. Use BOARD_WHEATLEY to distinguish them. Modified drivers: 1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I96198ffb6901f0539755046ca303e94381ae7541 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/320641 Reviewed-by: Randall Spangler <rspangler@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly