Randall Spangler af2c11e3e3 stm32: Flush UART buffer before changing EC core clock speed ...

Otherwise UART output gets garbled because there's a delay between
changing core clock and the UART divider.  Fortunately, the glitch is
cosmetic and doesn't affect proper EC operation.

BUG=chrome-os-partner:23982
BRANCH=none
TEST=power on, power off on pit or nyan --> no UART glitch

Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177087
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>

2013-11-19 18:30:16 +00:00

..

host

cleanup: Still more TODO comments

2013-11-02 01:07:10 +00:00

lm4

lm4: allow the lpc module to use GPIO for SCI

2013-11-15 01:39:42 +00:00

stm32

stm32: Flush UART buffer before changing EC core clock speed

2013-11-19 18:30:16 +00:00