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stm32: Flush UART buffer before changing EC core clock speed

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Otherwise UART output gets garbled because there's a delay between
changing core clock and the UART divider.  Fortunately, the glitch is
cosmetic and doesn't affect proper EC operation.

BUG=chrome-os-partner:23982
BRANCH=none
TEST=power on, power off on pit or nyan --> no UART glitch

Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177087
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
This commit is contained in:
Randall Spangler
2013-11-15 16:59:10 -08:00
committed by chrome-internal-fetch
parent 082d8b2e2d
commit af2c11e3e3
1 changed files with 7 additions and 1 deletions
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8
chip/stm32/clock-stm32l.c
View File

@@ -148,8 +148,14 @@ void clock_enable_module(enum module_id module, int enable)
new_mask = clock_mask & ~(1 << module);
/* Only change clock if needed */
if ((!!new_mask) != (!!clock_mask))
if ((!!new_mask) != (!!clock_mask)) {
/* Flush UART before switching clock speed */
cflush();
clock_set_osc(new_mask ? OSC_HSI : OSC_MSI);
}
clock_mask = new_mask;
}