Jiafei Pan b4ad976844 fix instruction address range limitation ...

For the adr instruction, it require the label's offset from the
address of this instruction must be in the range +/-1MB. If the
option "BL2_IN_XIP_MEM" is set to '1', in some cases, BL2's RW
memory will not in the range of +/-1MB from BL2's RO memory region.
so we need to use ldr instruction to cover this case.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

2018-04-07 10:13:59 +08:00

..

bl1

Fix MISRA rule 8.4 Part 1

2018-02-28 17:19:55 +00:00

bl2

Fix MISRA rule 8.4 Part 1

2018-02-28 17:19:55 +00:00

bl2u

Fix MISRA rule 8.4 in common code

2018-02-28 17:18:46 +00:00

bl31

Merge pull request #1282 from robertovargas-arm/misra-changes

2018-02-28 18:53:30 +00:00

bl32

Introduce the new BL handover interface

2018-02-26 16:31:10 +00:00

common

fix instruction address range limitation

2018-04-07 10:13:59 +08:00

drivers

Merge pull request #1334 from michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console

2018-04-03 11:59:55 +01:00

lib

Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements

2018-03-29 13:20:05 +01:00

plat

Add support for BL2 in XIP memory

2018-04-07 10:12:21 +08:00

services

Clean usage of void pointers to access symbols

2018-03-27 13:20:27 +01:00

tools_share

Dynamic cfg: Update the tools

2018-02-26 16:31:10 +00:00