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b4d996a5ea
The SCB registers are defined in the ARMv7-M architecture, so they are common to all chips. We will need System Control Register (SCR aka SYSCTRL) to implement power management on stm32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=snow Change-Id: I35c283731306541b3d21398c96fdca89954fe20a Reviewed-on: https://gerrit.chromium.org/gerrit/25392 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
- EC Lib
This wraps Blizzard driverlib and implements the EC chip interface defined
by Google. See below diagram for architecture.
+--------------------+
| Host BIOS/OS |
+--------------------+
---- host interface ----
+--------------------+
| Google EC features |
+--------------------+
---- chip interface ---- The interface is defined in
src/platform/ec/chip_interface/*.
+--------------------+ But the real implementation is in EC Lib.
| EC Lib |
+--------------------+
| Blizzard low level |
| driver, the |
| driverlib. |
+--------------------+