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0f73a129b4
The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
41 lines
1.0 KiB
C
41 lines
1.0 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Watchdog common code */
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#include "common.h"
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#include "panic.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "watchdog.h"
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void watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
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{
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uint32_t psp;
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uint32_t *stack;
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asm("mrs %0, psp" : "=r"(psp));
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if ((excep_lr & 0xf) == 1) {
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/* we were already in exception context */
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stack = (uint32_t *)excep_sp;
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} else {
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/* we were in task context */
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stack = (uint32_t *)psp;
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}
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panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ",
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stack[6], stack[5], psp);
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if ((excep_lr & 0xf) == 1)
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panic_puts("(exc) ###\n");
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else
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panic_printf("(task %d) ###\n", task_get_current());
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/* If we are blocked in a high priority IT handler, the following debug
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* messages might not appear but they are useless in that situation. */
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timer_print_info();
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task_print_list();
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}
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