OpenCellular

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Anton Staaf fba4f335a9 cortex-m0: Constrain target register in atomic read

One more register constaint needed to be added to the cortex-m0 atomic
inline assembly.  Vincent fixed all the others.  The requirement for
ARMv6-m includes that the target load register be one of the low
registers as well.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e
Reviewed-on: https://chromium-review.googlesource.com/292435
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>

2015-08-11 19:52:40 +00:00

atomic.h

cortex-m0: Constrain target register in atomic read

2015-08-11 19:52:40 +00:00

build.mk

Add option to enable GCC LTO

2015-05-19 02:46:27 +00:00

config_core.h

cleanup: fix all the header guards

2015-06-18 19:07:00 +00:00

cpu.c

cortex-m0: Add deferred scheduler