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One more register constaint needed to be added to the cortex-m0 atomic inline assembly. Vincent fixed all the others. The requirement for ARMv6-m includes that the target load register be one of the low registers as well. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e Reviewed-on: https://chromium-review.googlesource.com/292435 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Atomic operations for ARMv6-M */
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#ifndef __CROS_EC_ATOMIC_H
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#define __CROS_EC_ATOMIC_H
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#include "common.h"
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/**
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* Implements atomic arithmetic operations on 32-bit integers.
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*
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* There is no load/store exclusive on ARMv6-M, just disable interrupts
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*/
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#define ATOMIC_OP(asm_op, a, v) do { \
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uint32_t reg0; \
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\
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__asm__ __volatile__(" cpsid i\n" \
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" ldr %0, [%1]\n" \
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#asm_op" %0, %0, %2\n" \
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" str %0, [%1]\n" \
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" cpsie i\n" \
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: "=&b" (reg0) \
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: "b" (a), "r" (v) : "cc"); \
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} while (0)
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static inline void atomic_clear(uint32_t volatile *addr, uint32_t bits)
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{
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ATOMIC_OP(bic, addr, bits);
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}
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static inline void atomic_or(uint32_t volatile *addr, uint32_t bits)
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{
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ATOMIC_OP(orr, addr, bits);
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}
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static inline void atomic_add(uint32_t volatile *addr, uint32_t value)
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{
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ATOMIC_OP(add, addr, value);
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}
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static inline void atomic_sub(uint32_t volatile *addr, uint32_t value)
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{
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ATOMIC_OP(sub, addr, value);
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}
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static inline uint32_t atomic_read_clear(uint32_t volatile *addr)
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{
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uint32_t ret;
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__asm__ __volatile__(" mov %2, #0\n"
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" cpsid i\n"
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" ldr %0, [%1]\n"
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" str %2, [%1]\n"
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" cpsie i\n"
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: "=&b" (ret)
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: "b" (addr), "r" (0) : "cc");
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return ret;
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}
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#endif /* __CROS_EC_ATOMIC_H */
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