Duncan Laurie 466675fb17 skylake: Better handling of S0->S5->S0 path ...

If we are doing a cold reset or if Deep S5 is disabled we will go into S5
and need to be able to power up again, but we do not have enough information
to know what direction the sequencing may go from S5 (to G3 or up to S0).
So limit the RTCRST check to just the explicit G3->S5 path and let the normal
checking of SLP_S4 signal happen otherwise.

BUG=chrome-os-partner:49564
BRANCH=glados
TEST=pass FAFT testing finally

Change-Id: I202234e58281e6b007ad2b98396994222d0831b2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-01-22 11:55:56 -08:00

..

baytrail.c

power: Move EC_CMD_GSV_PAUSE_IN_S5 handler to common code

2015-05-07 17:25:40 +00:00

braswell.c

strago: Power state transition in case of apshutdown

2015-08-11 19:52:35 +00:00

build.mk

Remove obsolete board-specific code

2015-06-10 18:24:05 +00:00

common.c

Power: Use gpio_get_name instead of gpio_list

2016-01-19 14:24:35 -08:00

ec_driven.c

ryu: add a dummy power module for controlling sensors.

2014-11-18 05:19:47 +00:00

gaia.c

Add cprints() and ccprints()

2014-05-21 20:32:17 +00:00

haswell.c

power: Move EC_CMD_GSV_PAUSE_IN_S5 handler to common code

2015-05-07 17:25:40 +00:00

mediatek.c

oak: cancel long press timer when lost power_good or entering S3

2015-11-04 07:08:49 -08:00

rockchip.c

oak: enable MBKP events for PD events

2015-08-31 22:59:52 -07:00

skylake.c

skylake: Better handling of S0->S5->S0 path

2016-01-22 11:55:56 -08:00

tegra.c

tegra: enable EC sleep in S3

2015-06-26 20:17:45 +00:00