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The ACOK buffer from EC to PCH was not being triggered when the chipset powers up or down, instead it was only triggering when AC state was changed. Since we want it to be driven in S5 I added HOOK_CHIPSET_PRE_INIT to the power sequence in the G3S5 state transition. BUG=chrome-os-partner:23752 BRANCH=none TEST=power on samus proto1b with AC inserted and see PCH_ACOK go high, power off and see it go low again. Ensure that it is also changed with AC state transitions. Change-Id: I4cbe123322e234dc07f10fd1cdff5a8b771a4e02 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176630 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In the most general case, the flash layout looks something like this: +---------------------+ | Reserved for EC use | +---------------------+ +---------------------+ | Vblock B | +---------------------+ | RW firmware B | +---------------------+ +---------------------+ | Vblock A | +---------------------+ | RW firmware A | +---------------------+ +---------------------+ | FMAP | +---------------------+ | Public root key | +---------------------+ | Read-only firmware | +---------------------+ BIOS firmware (and kernel) put the vblock info at the start of each image where it's easy to find. The Blizzard EC expects the firmware vector table to come first, so we have to put the vblock at the end. This means we have to know where to look for it, but that's built into the FMAP and the RO firmware anyway, so that's not an issue. The RO firmware doesn't need a vblock of course, but it does need some reserved space for vboot-related things. Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If we reserve 4K at the top of each FW image, that should give us plenty of room for vboot-related stuff.