OpenCellular

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Caveh Jalali bee58e5d3e npcx: set eSPI speed to max supported by hardware

the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up
to 66MHz.  so, set the max speed to whatever the hardware can actually
do.  the bit pattern for 66MHz is "reserved" on the npcx7, so let's
not even define it in the npcx7 case.

BUG=b:72838699, b:71859563
BRANCH=none
TEST="make buildall" passes; boots on meowth

Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910321
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

2018-02-15 00:10:45 -08:00

g: protect flash operations

2018-01-31 13:47:15 -08:00

host

test: store persistence files in RAM

2018-01-31 05:58:03 -08:00

ish

ish i2c: use i2c_ports[] to set bus speed

2017-12-13 00:32:23 -08:00

it83xx

it83xx: espi: workaround for changing PLL

2017-12-12 22:00:36 -08:00