it83xx: espi: workaround for changing PLL

We need to change PLL settings if host apply eSPI operating
frequency higher than 50MHz, because FND clock is required
to be higher than half of operating frequency.

BRANCH=none
BUG=b:70537592
TEST=Change PLL succeed with chip select is low.

Change-Id: Ieba62f33ed024aed7a8e7f4cc48b1398ed781170
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/817717
Reviewed-by: Randall Spangler <rspangler@chromium.org>

chip/it83xx/clock.c

@@ -193,8 +193,20 @@ static void clock_set_pll(enum pll_freq_idx idx)
 		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
 				1, 1, 5, 1, 0);
 		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
+#ifdef CONFIG_ESPI
+		/*
+		 * Workaround for (b:70537592):
+		 * We have to set chip select pin as input mode in order to
+		 * change PLL.
+		 */
+		IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7);
+#endif
 		/* Update PLL settings. */
 		clock_pll_changed();
+#ifdef CONFIG_ESPI
+		/* (b:70537592) Change back to ESPI CS# function. */
+		IT83XX_GPIO_GPCRM5 &= ~0xc0;
+#endif
 	}
 
 	/* Get new/current setting of PLL frequency */

chip/it83xx/espi.c

@@ -367,11 +367,6 @@ void espi_init(void)
 {
 	int i;
 
-	/* TODO: PLL change won't success if eSPI chip select is low. */
-#if (PLL_CLOCK != 48000000)
-#error "Not support PLL change if eSPI module is enabled. "
-#endif
-
 	for (i = 0; i < ARRAY_SIZE(vw_init_setting); i++)
 		IT83XX_ESPI_VWIDX(vw_init_setting[i].index) =
 			(vw_init_setting[i].level_mask |

chip/it83xx/registers.h

@@ -613,6 +613,8 @@
 #define IT83XX_GPIO_GPCRI6      REG8(IT83XX_GPIO_BASE+0x56)
 #define IT83XX_GPIO_GPCRI7      REG8(IT83XX_GPIO_BASE+0x57)
 
+#define IT83XX_GPIO_GPCRM5      REG8(IT83XX_GPIO_BASE+0xA5)
+
 #define IT83XX_GPIO_GPDMRA      REG8(IT83XX_GPIO_BASE+0x61)
 #define IT83XX_GPIO_GPDMRB      REG8(IT83XX_GPIO_BASE+0x62)
 #define IT83XX_GPIO_GPDMRC      REG8(IT83XX_GPIO_BASE+0x63)