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c07c76e9ca
-Routing HPET1 timer requires HPET's General Config register's Legacy
routing bit should be set.
-For HPET0 interrupt, no need to set IRQ# to T0C register.
-change IRQ# back to default values.
BUG=None
BRANCH=master
TEST=`Build ISH and verify the timer interrupt via various
console cmds`
Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/627628
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver - HPET */
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#include "console.h"
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#include "hpet.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
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#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
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#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
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static uint32_t last_deadline;
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/* TODO: Conform to EC API
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* ISH supports 32KHz and 12MHz clock sources.
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* EC expects timer value in 1MHz.
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* Scale the values and support it.
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*/
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void __hw_clock_event_set(uint32_t deadline)
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{
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last_deadline = deadline;
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HPET_TIMER_COMP(1) = deadline;
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HPET_TIMER_CONF_CAP(1) |= HPET_Tn_INT_ENB_CNF;
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}
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uint32_t __hw_clock_event_get(void)
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{
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return last_deadline;
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}
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void __hw_clock_event_clear(void)
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{
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HPET_TIMER_CONF_CAP(1) &= ~HPET_Tn_INT_ENB_CNF;
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}
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uint32_t __hw_clock_source_read(void)
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{
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return HPET_MAIN_COUNTER;
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
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HPET_MAIN_COUNTER = ts;
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HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
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}
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static void __hw_clock_source_irq(int timer_id)
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{
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/* Clear interrupt */
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HPET_INTR_CLEAR = (1 << timer_id);
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/* If IRQ is from timer 0, 32-bit timer overflowed */
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process_timers(timer_id == 0);
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}
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void __hw_clock_source_irq_0(void)
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{
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__hw_clock_source_irq(0);
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}
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DECLARE_IRQ(ISH_HPET_TIMER0_IRQ, __hw_clock_source_irq_0);
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void __hw_clock_source_irq_1(void)
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{
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__hw_clock_source_irq(1);
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}
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DECLARE_IRQ(ISH_HPET_TIMER1_IRQ, __hw_clock_source_irq_1);
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int __hw_clock_source_init(uint32_t start_t)
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{
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/*
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* The timer can only fire interrupt when its value reaches zero.
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* Therefore we need two timers:
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* - Timer 0 as free running timer
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* - Timer 1 as event timer
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*/
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uint32_t timer0_config = 0x00000000;
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uint32_t timer1_config = 0x00000000;
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/* Disable HPET */
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HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
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HPET_MAIN_COUNTER = start_t;
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/* Set comparator value */
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HPET_TIMER_COMP(0) = 0XFFFFFFFF;
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/* Timer 0 - enable periodic mode */
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timer0_config |= HPET_Tn_TYPE_CNF;
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timer0_config |= HPET_Tn_32MODE_CNF;
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timer0_config |= HPET_Tn_VAL_SET_CNF;
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/* Timer 0 - IRQ routing, no need IRQ set for HPET0 */
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timer0_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
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/* Timer 1 - IRQ routing */
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timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
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timer1_config |= (ISH_HPET_TIMER1_IRQ <<
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HPET_Tn_INT_ROUTE_CNF_SHIFT);
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/* Level triggered interrupt */
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timer0_config |= HPET_Tn_INT_TYPE_CNF;
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timer1_config |= HPET_Tn_INT_TYPE_CNF;
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/* Enable interrupt */
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timer0_config |= HPET_Tn_INT_ENB_CNF;
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timer1_config |= HPET_Tn_INT_ENB_CNF;
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/* Unask HPET IRQ in IOAPIC */
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task_enable_irq(ISH_HPET_TIMER0_IRQ);
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task_enable_irq(ISH_HPET_TIMER1_IRQ);
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/* Set timer 0/1 config */
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HPET_TIMER_CONF_CAP(0) |= timer0_config;
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HPET_TIMER_CONF_CAP(1) |= timer1_config;
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#if defined CONFIG_ISH_40
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/* Wait for timer to settle. required for ISH 4 */
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while (HPET_CTRL_STATUS & HPET_T_CONF_CAP_BIT)
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;
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#endif
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/*
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* LEGACY_RT_CNF for HPET1 interrupt routing
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* and enable overall HPET counter/interrupts.
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*/
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HPET_GENERAL_CONFIG |= (HPET_ENABLE_CNF | HPET_LEGACY_RT_CNF);
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return ISH_HPET_TIMER1_IRQ;
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}
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