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4b3c13ddfe
MEC1322 use external spi rom. Now, we support W25X40 and W25Q64. Celes will use GD25Q41B for external EC ROM. So, we need to add define for GD25Q41B. BUG=chrome-os-partner:45246 BRANCH=master TEST=emerge-strago chromeos-ec Change-Id: Idec79955306b2dd79027fa57afc15ed8474413e6 Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/299576 Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.com> Tested-by: Jongpil Jung <jongpil19.jung@samsung.com> Reviewed-by: Shawn N <shawnn@chromium.org>
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/*
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* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* SPI flash protection register translation functions for Chrome OS EC.
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*/
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#ifndef __CROS_EC_SPI_FLASH_REG_H
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#define __CROS_EC_SPI_FLASH_REG_H
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#include "common.h"
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/*
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* Common register bits for SPI flash. All registers / bits may not be valid
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* for all parts.
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*/
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#define SPI_FLASH_SR2_SUS (1 << 7)
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#define SPI_FLASH_SR2_CMP (1 << 6)
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#define SPI_FLASH_SR2_LB3 (1 << 5)
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#define SPI_FLASH_SR2_LB2 (1 << 4)
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#define SPI_FLASH_SR2_LB1 (1 << 3)
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#define SPI_FLASH_SR2_QE (1 << 1)
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#define SPI_FLASH_SR2_SRP1 (1 << 0)
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#define SPI_FLASH_SR1_SRP0 (1 << 7)
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#define SPI_FLASH_SR1_SEC (1 << 6)
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#define SPI_FLASH_SR1_TB (1 << 5)
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#define SPI_FLASH_SR1_BP2 (1 << 4)
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#define SPI_FLASH_SR1_BP1 (1 << 3)
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#define SPI_FLASH_SR1_BP0 (1 << 2)
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#define SPI_FLASH_SR1_WEL (1 << 1)
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#define SPI_FLASH_SR1_BUSY (1 << 0)
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/* SR2 register existence based upon chip */
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#ifdef CONFIG_SPI_FLASH_W25X40
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#undef CONFIG_SPI_FLASH_HAS_SR2
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#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B)
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#define CONFIG_SPI_FLASH_HAS_SR2
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#endif
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/**
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* Computes block write protection range from registers
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* Returns start == len == 0 for no protection
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*
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* @param sr1 Status register 1
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* @param sr2 Status register 2
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* @param start Output pointer for protection start offset
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* @param len Output pointer for protection length
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
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unsigned int *len);
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/**
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* Computes block write protection registers from range
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*
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* @param start Desired protection start offset
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* @param len Desired protection length
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* @param sr1 Output pointer for status register 1
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* @param sr2 Output pointer for status register 2
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*
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* @return EC_SUCCESS, or non-zero if any error.
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*/
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int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
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uint8_t *sr2);
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#endif /* __CROS_EC_SPI_FLASH_REG_H */
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