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Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I3b77cbbb7f0cc12a4daae7ababd603b5d7af32d1
99 lines
4.3 KiB
C
99 lines
4.3 KiB
C
/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* GPIO module for Chrome EC */
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#ifndef __CROS_EC_GPIO_H
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#define __CROS_EC_GPIO_H
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#include "common.h"
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/* GPIO signal definitions. */
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/* TODO: the exact list is board-depdendent */
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enum gpio_signal {
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/* Inputs with interrupt handlers are first for efficiency */
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GPIO_POWER_BUTTONn = 0, /* Power button */
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GPIO_LID_SWITCHn, /* Lid switch */
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GPIO_POWER_ONEWIRE, /* 1-wire interface to power adapter LEDs */
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GPIO_THERMAL_DATA_READYn, /* Data ready from I2C thermal sensor */
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/* Other inputs */
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GPIO_AC_PRESENT, /* AC power present */
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GPIO_PCH_BKLTEN, /* Backlight enable signal from PCH */
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GPIO_PCH_SLP_An, /* SLP_A# signal from PCH */
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GPIO_PCH_SLP_ME_CSW_DEVn, /* SLP_ME_CSW_DEV# signal from PCH */
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GPIO_PCH_SLP_S3n, /* SLP_S3# signal from PCH */
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GPIO_PCH_SLP_S4n, /* SLP_S4# signal from PCH */
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GPIO_PCH_SLP_S5n, /* SLP_S5# signal from PCH */
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GPIO_PCH_SLP_SUSn, /* SLP_SUS# signal from PCH */
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GPIO_PCH_SUSWARNn, /* SUSWARN# signal from PCH */
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GPIO_PGOOD_1_5V_DDR, /* Power good on +1.5V_DDR */
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GPIO_PGOOD_1_5V_PCH, /* Power good on +1.5V_PCH */
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GPIO_PGOOD_1_8VS, /* Power good on +1.8VS */
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GPIO_PGOOD_5VALW, /* Power good on +5VALW */
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GPIO_PGOOD_CPU_CORE, /* Power good on +CPU_CORE */
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GPIO_PGOOD_VCCP, /* Power good on +VCCP */
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GPIO_PGOOD_VCCSA, /* Power good on +VCCSA */
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GPIO_PGOOD_VGFX_CORE, /* Power good on +VGFX_CORE */
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GPIO_RECOVERYn, /* Recovery signal from servo */
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GPIO_USB1_STATUSn, /* USB charger port 1 status output */
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GPIO_USB2_STATUSn, /* USB charger port 2 status output */
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GPIO_WRITE_PROTECTn, /* Write protect input */
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/* Outputs */
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GPIO_CPU_PROCHOTn, /* Force CPU to think it's overheated */
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GPIO_DEBUG_LED, /* Debug LED */
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GPIO_ENABLE_1_5V_DDR, /* Enable +1.5V_DDR supply */
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GPIO_ENABLE_BACKLIGHT, /* Enable backlight power */
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GPIO_ENABLE_VCORE, /* Enable +CPU_CORE and +VGFX_CORE */
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GPIO_ENABLE_VS, /* Enable VS power supplies */
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GPIO_ENTERING_RW, /* Indicate when EC is entering RW code */
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GPIO_PCH_A20GATE, /* A20GATE signal to PCH */
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GPIO_PCH_DPWROK, /* DPWROK signal to PCH */
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GPIO_PCH_HDA_SDO, /* HDA_SDO signal to PCH; when high, ME
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* ignores security descriptor */
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GPIO_PCH_LID_SWITCHn, /* Lid switch output to PCH */
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GPIO_PCH_NMIn, /* Non-maskable interrupt pin to PCH */
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GPIO_PCH_PWRBTNn, /* Power button output to PCH */
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GPIO_PCH_PWROK, /* PWROK / APWROK signals to PCH */
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GPIO_PCH_RCINn, /* RCIN# signal to PCH */
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GPIO_PCH_RSMRSTn, /* Reset PCH resume power plane logic */
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GPIO_PCH_SMIn, /* System management interrupt to PCH */
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GPIO_PCH_SUSACKn, /* Acknowledge PCH SUSWARN# signal */
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GPIO_SHUNT_1_5V_DDR, /* Shunt +1.5V_DDR; may also enable +3V_TP
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* depending on stuffing. */
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GPIO_USB1_CTL1, /* USB charger port 1 CTL1 output */
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GPIO_USB1_CTL2, /* USB charger port 1 CTL2 output */
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GPIO_USB1_CTL3, /* USB charger port 1 CTL3 output */
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GPIO_USB1_ENABLE, /* USB charger port 1 enable */
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GPIO_USB1_ILIM_SEL, /* USB charger port 1 ILIM_SEL output */
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GPIO_USB2_CTL1, /* USB charger port 2 CTL1 output */
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GPIO_USB2_CTL2, /* USB charger port 2 CTL2 output */
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GPIO_USB2_CTL3, /* USB charger port 2 CTL3 output */
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GPIO_USB2_ENABLE, /* USB charger port 2 enable */
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GPIO_USB2_ILIM_SEL, /* USB charger port 2 ILIM_SEL output */
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/* Number of GPIOs; not an actual GPIO */
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GPIO_COUNT
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};
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/* Pre-initializes the module. This occurs before clocks or tasks are
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* set up. */
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int gpio_pre_init(void);
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/* Initializes the GPIO module. */
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int gpio_init(void);
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/* Functions should return an error if the requested signal is not
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* supported / not present on the board. */
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/* Gets the current value of a signal (0=low, 1=hi). */
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int gpio_get_level(enum gpio_signal signal);
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/* Sets the current value of a signal. Returns error if the signal is
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* not supported or is an input signal. */
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int gpio_set_level(enum gpio_signal signal, int value);
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#endif /* __CROS_EC_GPIO_H */
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