Vincent Palatin c55f094960 stm32: fix RTC configuration on STM32H7
The DBP bit needs to be set in the PWR_CR1 register before doing the RTC
configuration (in order to be able to right RTC registers).

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, dump the RTC_TR register and it is incrementing
every second, e.g. 'rw 0x58004000'.

Change-Id: I02dc6c6f1852ced934bccf3e401f4fdc1aad57d9
Reviewed-on: https://chromium-review.googlesource.com/941224
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2018-03-02 06:49:05 -08:00
2018-03-01 16:13:43 -08:00
2017-08-07 19:29:13 -07:00
2017-07-08 20:38:53 -07:00
2017-10-10 22:13:43 -07:00
2018-02-28 15:21:08 -08:00
2018-02-23 23:12:58 -08:00
2012-05-11 09:11:52 -07:00
2014-04-02 19:58:53 +00:00
2017-11-16 21:07:40 -08:00

For an overview of the Embedded Controller firmware, refer to

http://www.chromium.org/chromium-os/2014-firmware-summit

For instructions on building from source, refer to

http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly
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