mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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d09526a63e
When the EC is busy enough to start missing RX characters an ORECF might come (Overrun error), we never check for this bit, so that means the interrupt handler will be called in a loop because it never clears that bit. This disables the overrun detection feature. BUG=chrome-os-partner:33451 TEST=get firmware to poll the EC for keyboard presses, type really fast on the keyboard, note how system does not watchdog reset anymore but loses the occasional character instead. BRANCH=None Change-Id: I711483768e4ba80aaeb4a324c7dee790b3a23682 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/236088 Reviewed-by: Randall Spangler <rspangler@chromium.org>
341 lines
8.0 KiB
C
341 lines
8.0 KiB
C
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USART driver for Chrome EC */
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#include "common.h"
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#include "clock.h"
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#include "dma.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "uart.h"
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#include "util.h"
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/* Console USART index */
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#define UARTN CONFIG_UART_CONSOLE
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#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
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#ifdef CONFIG_UART_TX_DMA
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#define UART_TX_INT_ENABLE STM32_USART_CR1_TCIE
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#ifndef CONFIG_UART_TX_DMA_CH
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#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
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#endif
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/* DMA channel options; assumes UART1 */
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static const struct dma_option dma_tx_option = {
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CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE),
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STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
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};
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#else
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#define UART_TX_INT_ENABLE STM32_USART_CR1_TXEIE
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#endif
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#ifdef CONFIG_UART_RX_DMA
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#ifndef CONFIG_UART_RX_DMA_CH
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#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART1_RX
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#endif
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/* DMA channel options; assumes UART1 */
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static const struct dma_option dma_rx_option = {
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CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE),
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STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
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STM32_DMA_CCR_CIRC
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};
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static int dma_rx_len; /* Size of receive DMA circular buffer */
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#endif
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static int init_done; /* Initialization done? */
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static int should_stop; /* Last TX control action */
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int uart_init_done(void)
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{
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return init_done;
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}
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void uart_tx_start(void)
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{
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/* If interrupt is already enabled, nothing to do */
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if (STM32_USART_CR1(UARTN_BASE) & UART_TX_INT_ENABLE)
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return;
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disable_sleep(SLEEP_MASK_UART);
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should_stop = 0;
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STM32_USART_CR1(UARTN_BASE) |= UART_TX_INT_ENABLE |
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STM32_USART_CR1_TCIE;
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task_trigger_irq(STM32_IRQ_USART(UARTN));
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}
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void uart_tx_stop(void)
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{
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STM32_USART_CR1(UARTN_BASE) &= ~UART_TX_INT_ENABLE;
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should_stop = 1;
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#ifdef CONFIG_UART_TX_DMA
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enable_sleep(SLEEP_MASK_UART);
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#endif
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}
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void uart_tx_flush(void)
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{
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while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE))
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;
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}
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int uart_tx_ready(void)
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{
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return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE;
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}
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#ifdef CONFIG_UART_TX_DMA
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int uart_tx_dma_ready(void)
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{
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return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC;
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}
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void uart_tx_dma_start(const char *src, int len)
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{
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/* Prepare DMA */
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dma_prepare_tx(&dma_tx_option, len, src);
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/* Force clear TC so we don't re-interrupt */
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STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC;
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/* Enable TCIE (chrome-os-partner:28837) */
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STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TCIE;
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/* Start DMA */
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dma_go(dma_get_channel(dma_tx_option.channel));
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}
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#endif /* CONFIG_UART_TX_DMA */
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int uart_rx_available(void)
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{
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return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_RXNE;
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}
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#ifdef CONFIG_UART_RX_DMA
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void uart_rx_dma_start(char *dest, int len)
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{
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/* Start receiving */
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dma_rx_len = len;
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dma_start_rx(&dma_rx_option, len, dest);
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}
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int uart_rx_dma_head(void)
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{
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return dma_bytes_done(dma_get_channel(CONFIG_UART_RX_DMA_CH),
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dma_rx_len);
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}
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#endif
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void uart_write_char(char c)
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{
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/* Wait for space */
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while (!uart_tx_ready())
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;
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STM32_USART_TDR(UARTN_BASE) = c;
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}
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int uart_read_char(void)
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{
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return STM32_USART_RDR(UARTN_BASE);
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}
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void uart_disable_interrupt(void)
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{
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task_disable_irq(STM32_IRQ_USART(UARTN));
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}
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void uart_enable_interrupt(void)
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{
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task_enable_irq(STM32_IRQ_USART(UARTN));
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}
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/* Interrupt handler for console USART */
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void uart_interrupt(void)
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{
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#ifndef CONFIG_UART_TX_DMA
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/*
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* When trasmission completes, enable sleep if we are done with Tx.
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* After that, proceed if there is other interrupt to handle.
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*/
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if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) {
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if (should_stop) {
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STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
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enable_sleep(SLEEP_MASK_UART);
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}
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STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC;
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if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC))
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return;
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}
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#endif
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#ifdef CONFIG_UART_TX_DMA
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/* Disable transmission complete interrupt if DMA done */
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if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC)
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STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE;
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#else
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/*
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* Disable the TX empty interrupt before filling the TX buffer since it
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* needs an actual write to DR to be cleared.
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*/
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STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TXEIE;
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#endif
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#ifndef CONFIG_UART_RX_DMA
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/*
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* Read input FIFO until empty. DMA-based receive does this from a
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* hook in the UART buffering module.
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*/
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uart_process_input();
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#endif
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/* Fill output FIFO */
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uart_process_output();
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#ifndef CONFIG_UART_TX_DMA
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/*
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* Re-enable TX empty interrupt only if it was not disabled by
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* uart_process_output().
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*/
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if (!should_stop)
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STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TXEIE;
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#endif
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}
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DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2);
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/**
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* Handle clock frequency changes
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*/
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static void uart_freq_change(void)
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{
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int freq;
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int div;
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#if (defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)) && \
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(UARTN <= 2)
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/*
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* UART is clocked from HSI (8MHz) to allow it to work when waking
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* up from sleep
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*/
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freq = 8000000;
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#else
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/* UART clocked from the main clock */
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freq = clock_get_freq();
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#endif
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div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE);
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#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \
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defined(CHIP_FAMILY_STM32F3)
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if (div / 16 > 0) {
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/*
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* CPU clock is high enough to support x16 oversampling.
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* BRR = (div mantissa)<<4 | (4-bit div fraction)
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*/
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STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_OVER8;
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STM32_USART_BRR(UARTN_BASE) = div;
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} else {
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/*
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* CPU clock is low; use x8 oversampling.
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* BRR = (div mantissa)<<4 | (3-bit div fraction)
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*/
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STM32_USART_BRR(UARTN_BASE) = ((div / 8) << 4) | (div & 7);
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STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_OVER8;
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}
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#else
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/* STM32F only supports x16 oversampling */
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STM32_USART_BRR(UARTN_BASE) = div;
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#endif
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}
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DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT);
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void uart_init(void)
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{
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/* Enable USART clock */
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#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
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#if (UARTN == 1)
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STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */
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#elif (UARTN == 2)
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STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */
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#endif /* UARTN */
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#endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */
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#if (UARTN == 1)
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STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1;
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#else
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STM32_RCC_APB1ENR |= CONCAT2(STM32_RCC_PB1_USART, UARTN);
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#endif
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/* Configure GPIOs */
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gpio_config_module(MODULE_UART, 1);
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#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
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/*
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* Wake up on start bit detection. WUS can only be written when UE=0,
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* so clear UE first.
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*/
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STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE;
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/*
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* Also disable the RX overrun interrupt, since we don't care about it
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* and we don't want to clear an extra flag in the interrupt
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*/
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STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT |
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STM32_USART_CR3_OVRDIS;
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#endif
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/*
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* UART enabled, 8 Data bits, oversampling x16, no parity,
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* TX and RX enabled.
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*/
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STM32_USART_CR1(UARTN_BASE) =
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STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
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/* 1 stop bit, no fancy stuff */
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STM32_USART_CR2(UARTN_BASE) = 0x0000;
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#ifdef CONFIG_UART_TX_DMA
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/* Enable DMA transmitter */
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STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT;
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#else
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/* DMA disabled, special modes disabled, error interrupt disabled */
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STM32_USART_CR3(UARTN_BASE) &= ~STM32_USART_CR3_DMAR &
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~STM32_USART_CR3_DMAT &
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~STM32_USART_CR3_EIE;
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#endif
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#ifdef CONFIG_UART_RX_DMA
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/* Enable DMA receiver */
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STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAR;
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#else
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/* Enable receive-not-empty interrupt */
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STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_RXNEIE;
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#endif
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#ifdef CHIP_FAMILY_STM32L
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/* Use single-bit sampling */
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STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_ONEBIT;
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#endif
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/* Set initial baud rate */
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uart_freq_change();
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/* Enable interrupts */
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task_enable_irq(STM32_IRQ_USART(UARTN));
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init_done = 1;
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}
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