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stm32f0: USART: Disable ORECF interrupt we never check for

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When the EC is busy enough to start missing RX characters an ORECF might come
(Overrun error), we never check for this bit, so that means the interrupt
handler will be called in a loop because it never clears that bit.

This disables the overrun detection feature.

BUG=chrome-os-partner:33451
TEST=get firmware to poll the EC for keyboard presses, type really fast on the
keyboard, note how system does not watchdog reset anymore but loses the
occasional character instead.
BRANCH=None

Change-Id: I711483768e4ba80aaeb4a324c7dee790b3a23682
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236088
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Alexandru M Stan
2014-12-16 12:50:42 -08:00
committed by chrome-internal-fetch
parent 86835f7067
commit d09526a63e
3 changed files with 9 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
chip/stm32/registers.h
View File

@@ -194,6 +194,7 @@
#define STM32_USART_CR3_DMAR (1 << 6)
#define STM32_USART_CR3_DMAT (1 << 7)
#define STM32_USART_CR3_ONEBIT (1 << 11)
#define STM32_USART_CR3_OVRDIS (1 << 12)
#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
#define STM32_USART_CR3_WUFIE (1 << 22)
#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)

8
chip/stm32/uart.c
View File

@@ -288,7 +288,13 @@ void uart_init(void)
* so clear UE first.
*/
STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE;
STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT;
/*
* Also disable the RX overrun interrupt, since we don't care about it
* and we don't want to clear an extra flag in the interrupt
*/
STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT |
STM32_USART_CR3_OVRDIS;
#endif
/*

2
chip/stm32/usart.c
View File

@@ -89,7 +89,7 @@ void usart_init(struct usart_config const *config)
STM32_USART_CR1_RE |
STM32_USART_CR1_RXNEIE);
STM32_USART_CR2(base) = 0x0000;
STM32_USART_CR3(base) = 0x0000;
STM32_USART_CR3(base) = STM32_USART_CR3_OVRDIS;
/*
* Enable the variant specific HW.