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3424deb481
Since npcx5m6g has larger than 128 KB code ram for FW, the original alignment between RO & RW regions isn't suitable for new chip. Therefore, we add 256KB alignment of them for npcx5m6g. In order to program the flash used by npcx5m6g, we add new board array, BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g and flash_npcx5m6g to program flash with different layout. Modified sources: 1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for npcx5m6g. 2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to distinguish which flash layout ec used. 3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with different layout. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/331903 Reviewed-by: Shawn N <shawnn@chromium.org>