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ebd29d4557
We found the deviation of 115200 UART baud-rate is too large when core clock is 16 or 12MHz. It causes failure during FAFT since sometime EC could not receive correct commands to proceed test. We adjusted core clock from 16/12 to 15/13 to reduce the deviation of 115200. Both of them have run FAFT and stress tests for weeks and no UART issues were found. Since the lowest source clock of i2c is 6.5MHz, we modified tSCLL, tSCLH and hold time directly for better i2c timing when freq is 400K. And if freq is 100K, we introduced normal mode to handle it. Modified sources: 1. clock.c: Adjust core clock from 16/12 MHz to 15/13 MHz. 2. clock_chip.h: Set target core clock as 15 MHz. 3. uart.c: Add baud-rate support for 15/13 MHz. 4. register.h: Add new register definitions of SMBus. 5. i2c.c: Modified tSCLL, tSCLH and hold time directly for better i2c timing. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ie5d22e87875c064b49338046c99a178f8fadf32b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/322320 Reviewed-by: Shawn N <shawnn@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly