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ed30a9ea11
LPC and eSPI logical device configuration is mostly common. Create common subroutines for LD configuration. Fix bugs in LPC LD configuration for ACPI, EMI, Port80. Add work- around for APL LRESET# changing when LPC clock is not running. BRANCH=none BUG=None TEST=Build all boards using chip mchp. Test LPC and eSPI communication with host chipset via EC/Host UART logs. CQ-DEPEND=CL:1053576,CL:1053827,CL:1053880,CL:1053949 Change-Id: Ie40245c20627178a0e518eafc028d194c1f176a6 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053884 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly