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ee86be472d
Except for the console UART TX and the SPI slave MISO, this CL configures all the formerly output GPIOs as inputs. The Cr50 firmware at this point doesn't actually DO anything useful with the GPIOs that would normally be outputs on the Kevin board (we don't assert SYS_RESET, or EC_FLASH_SELECT, for example), and the board *should* be designed so that no important signals like those just float. By using this configuration, we're trying to limit the potential harm done by unexpected schematic changes. Once the system boots, we should be able to use the SPI bus to update Cr50 to add more features, such as testing Cr50 GPIOs individually. BUG=chrome-os-partner:49952 BRANCH=none TEST=make buildall, run on Cr50 board Change-Id: I1f0a164e2cd3e4f632b862e33dba69f0dc944322 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329557 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>